- Aug 17, 2012
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Akira Hatanaka authored
No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
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Bill Wendling authored
<rdar://problem/10545247> llvm-svn: 162131
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Jakob Stoklund Olesen authored
PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
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Akira Hatanaka authored
Patch by Vladimir Medic. llvm-svn: 162124
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Benjamin Kramer authored
The previous fix only checked for simple cycles, use a set to catch longer cycles too. Drop the broken check from the ObjectSizeOffsetEvaluator. The BoundsChecking pass doesn't have to deal with invalid IR like InstCombine does. llvm-svn: 162120
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Bill Wendling authored
make it more consistent with its intended semantics. The `linker_private_weak_def_auto' linkage type was meant to automatically hide globals which never had their addresses taken. It has nothing to do with the `linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix among other things. The intended semantic is more like the `linkonce_odr' linkage type. Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore changing the semantics so that it produces the correct output for the linker. Note: The old linkage name `linker_private_weak_def_auto' will still parse but is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0. <rdar://problem/11754934> llvm-svn: 162114
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Rafael Espindola authored
multiple edges between two blocks is linear. If the caller is iterating all edges leaving a BB that would be a square time algorithm. It is more efficient to have the callers handle that case. Currently the only callers are: * GVN: already avoids the multiple edge case. * Verifier: could only hit this assert when looking at an invalid invoke. Since it already rejects the invoke, just avoid computing the dominance for it. llvm-svn: 162113
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Jakob Stoklund Olesen authored
llvm-svn: 162107
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Benjamin Kramer authored
TargetLowering: Use the large shift amount during legalize types. The legalizer may call us with an overly large type. llvm-svn: 162101
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Jakob Stoklund Olesen authored
Increment the MBB iterator at the top of the loop to properly handle the current (and previous) instructions getting erased. This fixes PR13625. llvm-svn: 162099
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Benjamin Kramer authored
Guard MemoryBuiltins against self-looping GEPs, which can occur in unreachable code due to constant propagation. Fixes PR13621. llvm-svn: 162098
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Benjamin Kramer authored
I really need to find a way to automate this, but I can't come up with a regex that has no false positives while handling tricky cases like custom check prefixes. llvm-svn: 162097
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Tim Northover authored
llvm-svn: 162094
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Jin-Gu Kang authored
Insertion of NoFolder functions to avoid ambiguous overload warnings or errors about whether to convert Idx to ArrayRef<Constant *> or ArrayRef<Value *> like ConstantFolder and TargetFolder. llvm-svn: 162090
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Craig Topper authored
llvm-svn: 162089
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Craig Topper authored
Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler. llvm-svn: 162088
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Pranav Bhandarkar authored
include/llvm/IntrinsicsHexagon.td: Hexagon_Intrinsic is the base class for all Hexagon intrinsics and not altivec intrinsics. llvm-svn: 162087
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Craig Topper authored
llvm-svn: 162086
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Craig Topper authored
llvm-svn: 162085
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Craig Topper authored
llvm-svn: 162082
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NAKAMURA Takumi authored
lit: Show actually created count of threads. The incorrect threads count is printed if the number of tests are less than the number of default threads. Thanks to Vinson Lee, reported in PR13620. llvm-svn: 162078
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Chandler Carruth authored
templated union at the request of Richard Smith. This makes it substantially easier to type. =] llvm-svn: 162072
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Jakob Stoklund Olesen authored
It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
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Jakob Stoklund Olesen authored
Use the target independent select analysis hooks. llvm-svn: 162060
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Jakob Stoklund Olesen authored
Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
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- Aug 16, 2012
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Roman Divacky authored
llvm-svn: 162039
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Roman Divacky authored
llvm-svn: 162037
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Roman Divacky authored
llvm-svn: 162035
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Roman Divacky authored
llvm-svn: 162034
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Roman Divacky authored
llvm-svn: 162032
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Rafael Espindola authored
where some fact lake a=b dominates a use in a phi, but doesn't dominate the basic block itself. This feature could also be implemented by splitting critical edges, but at least with the current algorithm reasoning about the dominance directly is faster. The time for running "opt -O2" in the testcase in pr10584 is 1.003 times slower and on gcc as a single file it is 1.0007 times faster. llvm-svn: 162023
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Nadav Rotem authored
llvm-svn: 162014
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Jush Lu authored
Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. llvm-svn: 162013
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Anitha Boyapati authored
llvm-svn: 162012
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Anitha Boyapati authored
llvm-svn: 162010
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Akira Hatanaka authored
llvm-svn: 162009
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Akira Hatanaka authored
floats. llvm-svn: 162008
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Victor Oliveira authored
llvm-svn: 161995
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Jakob Stoklund Olesen authored
The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
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- Aug 15, 2012
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Bill Wendling authored
llvm-svn: 161990
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