llvm-svn: 55577

llvm-svn: 55576

   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)

llvm-svn: 55575

llvm-svn: 55574

llvm-svn: 55571

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

llvm-svn: 55564

llvm-svn: 55563

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555

llvm-svn: 55551

llvm-svn: 55549

llvm-svn: 55512

llvm-svn: 55504

llvm-svn: 55500

its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498

SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

llvm-svn: 55497

were being emitted after the first instructions of the entry block.

llvm-svn: 55496

llvm-svn: 55483

Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

llvm-svn: 55482

FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

llvm-svn: 55476

Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475

llvm-svn: 55471

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457

works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

llvm-svn: 55450

llvm-svn: 55439

llvm-svn: 55434

llvm-svn: 55431

llvm-svn: 55430

Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

llvm-svn: 55428

just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

llvm-svn: 55427

the details of materializing constants and other values into
registers, and make use of it in several places.

llvm-svn: 55426

llvm-svn: 55425

of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.

llvm-svn: 55421

a scratch std::vector.

llvm-svn: 55420

which isn't needed anymore.

llvm-svn: 55419

llvm-svn: 55401

llvm-svn: 55400

llvm-svn: 55399

This simultaneously makes the code simpler and adds support for sext as well.

llvm-svn: 55398