- Jun 09, 2012
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Jakob Stoklund Olesen authored
OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
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- Feb 17, 2012
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Jakob Stoklund Olesen authored
MRI keeps track of which physregs have been used. Make sure it gets updated with all the regmask-clobbered registers. Delete the closePhysRegsUsed() function which isn't necessary. llvm-svn: 150830
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- Jan 19, 2012
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Evan Cheng authored
llvm-svn: 148464
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- Jan 07, 2012
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Jakob Stoklund Olesen authored
llvm-svn: 147725
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- Jan 03, 2012
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Jakob Stoklund Olesen authored
This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
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- Nov 13, 2011
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Jakob Stoklund Olesen authored
This thing is looking a lot like a virtual register map now. llvm-svn: 144486
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Jakob Stoklund Olesen authored
Nobody cared, StackSlotColoring scans the instructions to find used stack slots. llvm-svn: 144485
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Jakob Stoklund Olesen authored
Most of this stuff was supporting the old deferred spill code insertion mechanism. Modern spillers just edit machine code in place. llvm-svn: 144484
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Jakob Stoklund Olesen authored
The information was only used by the register allocator in StackSlotColoring. llvm-svn: 144482
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- Oct 05, 2011
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Jakob Stoklund Olesen authored
For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. llvm-svn: 141139
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- Sep 15, 2011
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Jakob Stoklund Olesen authored
Fix the stats counters to reflect that. llvm-svn: 139819
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- May 06, 2011
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Jakob Stoklund Olesen authored
llvm-svn: 130996
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- Apr 27, 2011
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Jakob Stoklund Olesen authored
We cannot rely on the <imp-def> operands added by LiveIntervals in all cases as demonstrated by the test case. llvm-svn: 130313
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- Mar 31, 2011
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Jakob Stoklund Olesen authored
Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. llvm-svn: 128645
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- Mar 23, 2011
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Jakob Stoklund Olesen authored
llvm-svn: 128143
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- Feb 18, 2011
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Jakob Stoklund Olesen authored
The rewriter works almost identically to -rewriter=trivial, except it also eliminates any identity copies. This makes the new register allocators independent of VirtRegRewriter.cpp which will be going away at the same time as RegAllocLinearScan. llvm-svn: 125967
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- Jan 10, 2011
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Jakob Stoklund Olesen authored
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
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- Jan 09, 2011
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Jakob Stoklund Olesen authored
when no virtual registers have been allocated. It was only used to resize IndexedMaps, so provide an IndexedMap::resize() method such that Map.grow(MRI.getLastVirtReg()); can be replaced with the simpler Map.resize(MRI.getNumVirtRegs()); This works correctly when no virtuals are allocated, and it bypasses the to/from index conversions. llvm-svn: 123130
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Jakob Stoklund Olesen authored
Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
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Jakob Stoklund Olesen authored
depending on TRI::FirstVirtualRegister. Also use TRI::printReg instead of printing virtual registers directly. llvm-svn: 123101
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- Nov 16, 2010
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Jakob Stoklund Olesen authored
Use amazing new function call technology instead of writing identical code in multiple places. This fixes PR8604. llvm-svn: 119306
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- Oct 08, 2010
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Owen Anderson authored
llvm-svn: 115996
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- Jul 22, 2010
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Owen Anderson authored
llvm-svn: 109045
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- Feb 26, 2010
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Jakob Stoklund Olesen authored
The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
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- Feb 10, 2010
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Dan Gohman authored
llvm-svn: 95781
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- Jan 05, 2010
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David Greene authored
llvm-svn: 92587
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- Nov 12, 2009
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David Greene authored
Add a bool flag to StackObjects telling whether they reference spill slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
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- Nov 04, 2009
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Lang Hames authored
This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. llvm-svn: 85979
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- Oct 17, 2009
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Evan Cheng authored
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. llvm-svn: 84326
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- Aug 23, 2009
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Chris Lattner authored
llvm-svn: 79842
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- Jul 24, 2009
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Daniel Dunbar authored
LiveInterval, etc to raw_ostream. llvm-svn: 76965
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- Jun 15, 2009
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Evan Cheng authored
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
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- Jun 14, 2009
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Evan Cheng authored
Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
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- May 04, 2009
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Evan Cheng authored
llvm-svn: 70821
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- May 03, 2009
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Evan Cheng authored
In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants. Not yet enabled. This is part 1. More coming. llvm-svn: 70787
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- Mar 31, 2009
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Bill Wendling authored
llvm-svn: 68099
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Bill Wendling authored
llvm-svn: 68092
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- Mar 14, 2009
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Daniel Dunbar authored
llvm-svn: 67000
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- Mar 13, 2009
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Owen Anderson authored
llvm-svn: 66870
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- Mar 11, 2009
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Owen Anderson authored
Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files. No (intended) functionality change. llvm-svn: 66720
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