- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

llvm-svn: 73380

Patch by Benjamin Kramer!

llvm-svn: 73379

llvm-svn: 73373

llvm-svn: 73372

llvm-svn: 73369

absolute or not, based on a patch by Gregory Curfman!

llvm-svn: 73368

llvm-svn: 73366

llvm-svn: 73362

they contain multiplications of constants with add operations.
This helps simplify several kinds of things; in particular it
helps simplify expressions like ((-1 * (%a + %b)) + %a) to %b,
as expressions like this often come up in loop trip count
computations.

llvm-svn: 73361

used as keys in DenseMaps.

llvm-svn: 73360

the potentially expensive erase.

llvm-svn: 73359

even though the order doesn't matter at the top level of an expression,
it does matter when the constant is a subexpression of an n-ary
expression, because n-ary expressions are sorted lexicographically.

llvm-svn: 73358

SmallVector instead of std::vector.

llvm-svn: 73357

llvm-svn: 73355

llvm-svn: 73353

Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

llvm-svn: 73342

is that, for functions whose bodies are entirely guarded by an if-statement, it
can be profitable to pull the test out of the callee and into the caller.

This code has had some cursory testing, but still has a number of known issues
on the LLVM test suite.

llvm-svn: 73338

Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray

llvm-svn: 73333

llvm-svn: 73331

llvm-svn: 73320

pointer. This fixes kimwitu++. Pointed out by Frits van Bommel on review!

llvm-svn: 73299

The subprogram descriptor for a function may be missing (llvm-ld linking two static functions with same name), so pick up the compilation unit for the function from the first valid debug loc of its instructions.
This patch also emits debug info for structure (aggregate types in 
general) types.

llvm-svn: 73295

induction variable when the addrec to be expanded does not require
a wider type. This eliminates the need for IndVarSimplify to
micro-manage SCEV expansions, because SCEVExpander now
automatically expands them in the form that IndVarSimplify considers
to be canonical. (LSR still micro-manages its SCEV expansions,
because it's optimizing for the target, rather than for
other optimizations.)

Also, this uses the new getAnyExtendExpr, which has more clever
expression simplification logic than the IndVarSimplify code it
replaces, and this cleans up some ugly expansions in code such as
the included masked-iv.ll testcase.

llvm-svn: 73294

extension with unspecified bits.

llvm-svn: 73293

consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291

llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function.  If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available.  LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. 
Apply defensive patch to preserve at least one lexical scope till the end of function.

llvm-svn: 73282

llvm-svn: 73271

of the target's pointer size. This avoids the need for -m32 on
the llvm-gcc command-line, which some targets may not support.

llvm-svn: 73270

on systems which default to a 64-bit target.

llvm-svn: 73265

llvm-svn: 73258

llvm-svn: 73257

llvm-svn: 73256

If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.

llvm-svn: 73255

non-default addrspaces.

llvm-svn: 73253

llvm-svn: 73252

Document noredzone and noimplicitfloat function attributes.

llvm-svn: 73246

llvm-svn: 73244

it may round differently. This fixes PR4374.

llvm-svn: 73243