- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291

llvm-svn: 73252

llvm-svn: 73098

llvm-svn: 73097

ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095

llvm-svn: 73085

llvm-svn: 73080

llvm-svn: 72969

Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.

llvm-svn: 72955

llvm-svn: 72952

llvm-svn: 72950

llvm-svn: 72948

Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.

llvm-svn: 72826

llvm-svn: 72757

llvm-svn: 72756

llvm-svn: 72698

llvm-svn: 72697

llvm-svn: 72696

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631

llvm-svn: 72604

llvm-svn: 72593

llvm-svn: 72395

llvm-svn: 72337

llvm-svn: 72336

llvm-svn: 72335

for ARM.  This fixes rdar://6908807.

llvm-svn: 72269

llvm-svn: 72172

llvm-svn: 72138

This fixes pr4233.

llvm-svn: 72115

the stack.  Patch by Sandeep Patel.

llvm-svn: 72106

llvm-svn: 72105

to run last because it needs to know the exact size and position of every
basic block.  Currently CodePlacementOpt is set up to run last.  It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.

llvm-svn: 72037

llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758

llvm-svn: 71735

llvm-svn: 71726

booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722

a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610

llvm-svn: 71602

llvm-svn: 71563