llvm-svn: 103199

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

we don't currently support relaxing them.

llvm-svn: 103195

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128

llvm-svn: 103103

hack the code to turn it off when debugging.

llvm-svn: 103083

llvm-svn: 103057

instructions which have no direct register usage.

Darwin 'as' accepts:
  add $0, (%rax)
but rejects
  mov $0, (%rax)
for example.

Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...

llvm-svn: 103015

 - The idea is that when a match fails, we just try to match each of +'b', +'w',
   +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
   it. If all match, we assume it is width generic, and take the 'l' form.

 - This would be a horrible hack, if it weren't so simple. Therefore it is an
   elegant solution! Chris gets the credit for this particular elegant
   solution. :)

 - Next step to making this more robust is to have the X86 matcher generate the
   mnemonic prefix information. Ideally we would also compute up-front exactly
   which mnemonic to attempt to match, but this may require more custom code in
   the matcher than is really worth it.

llvm-svn: 103012

changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.

llvm-svn: 102991

instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.

llvm-svn: 102958

mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.

llvm-svn: 102952

caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.

llvm-svn: 102951

llvm-svn: 102941

changes before doing phi lowering for switches.

llvm-svn: 102809

on the original variables, so it's easier to see what is being done
to which blocks.

llvm-svn: 102759

llvm-svn: 102730

Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.

llvm-svn: 102683

print randomly in debug output.

llvm-svn: 102668

	##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0

llvm-svn: 102655

should use esp / rsp to reference frame instead.

llvm-svn: 102596

llvm-svn: 102577

Operand size override prefix to be part of their records.

llvm-svn: 102556

instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

llvm-svn: 102509

llvm-svn: 102493

llvm-svn: 102488

llvm-svn: 102486

Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).

llvm-svn: 102485

llvm-svn: 102477

llvm-svn: 102467

llvm-svn: 102456

otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400

llvm-svn: 102366

llvm-svn: 102326

- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323

form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.

llvm-svn: 102320