llvm-svn: 170660

Separate encoding information from the rest.

llvm-svn: 170659

This has undefined behavior, because the classof implementation attempts to
access parts of the not-yet-constructed derived class. Found by clang
-fsanitize=vptr.

llvm-svn: 170658

Separate encoding information from the rest.

llvm-svn: 170657

these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656

physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.

llvm-svn: 170655

llvm-svn: 170654

behavior and violates the !range constraints we put on loads of this enum.
Found by clang -fsanitize=enum.

llvm-svn: 170653

such a structure has undefined behavior. Caught by -fsanitize=bool.

llvm-svn: 170652

the end. 

llvm-svn: 170651

information from the rest.

llvm-svn: 170650

from the rest.

llvm-svn: 170649

Separate encoding information from the rest.

llvm-svn: 170648

information from the rest.

llvm-svn: 170647

This is a pretty lengthy document, so put the table of contents in your
face so that it's easier to scope out the content.

This document is a mess currently and needs to be
refactored/revised/split-up.

llvm-svn: 170646

ArithLogicI as the instruction base classes.

llvm-svn: 170642

For whatever reason the usage of '^^^' and '---' adornments were
reversed compared to the "canonical" style of the LLVM docs (which is
currently "the style used in SphinxQuickstartTemplate.rst"). This change
doesn't affect the document structure at all, I'm just doing it for
trivial stylistic consistency (the document content is *much* more
important---thanks Nadav for writing this up!).

Also, trim the adornments to be the same length as the section names.

llvm-svn: 170638

llvm-svn: 170637

llvm-svn: 170632

llvm-svn: 170631

<rdar://problem/12879313>

llvm-svn: 170630

llvm-svn: 170629

llvm-svn: 170628

llvm-svn: 170627

llvm-svn: 170626

llvm-svn: 170622

llvm-svn: 170620

llvm-svn: 170618

llvm-svn: 170615

MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

llvm-svn: 170610

isSub and isSuper return false if RegA == RegB. Add variants which also
include the identity function.

llvm-svn: 170609

These were defined on TargetRegisterInfo, but they don't use any information
that's not available in MCRegisterInfo, so sink them down to be available
at the MC layer.

llvm-svn: 170608

llvm-svn: 170607

Refactor isIntrinsic() to be quicker, and change classof() (and thus, isa<IntrinsicInst>()) to use it. This decreases the number of occurrences of the slow-path string matching performed by getIntrinsicID().

llvm-svn: 170602

llvm-svn: 170600

The single-argument MachineInstr::addOperand(MO) will be removed soon.

llvm-svn: 170599

No testcase because it is apparently not so trivial to construct.

llvm-svn: 170595

llvm-svn: 170594

Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170593

Branch if we have enough instructions so that it makes sense.
Also remove branches if they don't make sense.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170592