llvm-svn: 102456

otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400

Radar 7896289

llvm-svn: 102396

llvm-svn: 102373

DBG_VALUE, and a cautionary comment.

llvm-svn: 102371

llvm-svn: 102366

llvm-svn: 102326

llvm-svn: 102325

llvm-svn: 102324

- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323

form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.

llvm-svn: 102320

llvm-svn: 102237

alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206

llvm-svn: 102199

llvm-svn: 102192

extraction. This fixes PR5998.

llvm-svn: 102144

and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123

- Some code refactoring.

llvm-svn: 102111

llvm-svn: 102008

optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181

llvm-svn: 101984

llvm-svn: 101979

llvm-svn: 101978

llvm-svn: 101977

before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974

fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}

llvm-svn: 101965

(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958

user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)

llvm-svn: 101951

instead of just asserting.

llvm-svn: 101942

transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915

patch by Kalle Raiskila!

llvm-svn: 101875

an optimizer infinite loop on the file, PR6866.

llvm-svn: 101854

d==15 is considered illegal.  Return false instead of assert().

llvm-svn: 101852

shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851

llvm-svn: 101839

llvm-svn: 101827

llvm-svn: 101824

Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817

llvm-svn: 101808

instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788

VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784