Commits · 154a72ddf7500b6daf428b89254a9f087b05c333 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Jun 07, 2018
- Fix unused private variable. · 154a72dd
  Zachary Turner authored Jun 07, 2018
  154a72dd
- [InstSimplify] shl nuw C, %x -> C iff signbit is set on C. · 2683802b
  Roman Lebedev authored Jun 07, 2018
  2683802b
- [FileSystem] Split up the OpenFlags enumeration. · 1f67a3cb
  Zachary Turner authored Jun 07, 2018
  1f67a3cb
- DAG: Avoid bitcast/ext/build_vector combine · e8eb567e
  Matt Arsenault authored Jun 07, 2018
  e8eb567e
- [TargetLibraryInfo] add mappings from LLVM sin/cos intrinsics to SVML calls · 4b1205b4
  Sanjay Patel authored Jun 07, 2018
  4b1205b4
- [LSR] Check yet more intrinsic pointer operands · 12c0663a
  Daniil Fukalov authored Jun 07, 2018
  12c0663a
- [X86][SSE] Updated comment - combineVectorSignBitsTruncation handles PACKSS and PACKUS. NFCI. · 51ceef77
  Simon Pilgrim authored Jun 07, 2018
  51ceef77
- [RISCV] AsmParser support for the li pseudo instruction · 6a4b5441
  Alex Bradbury authored Jun 07, 2018
  6a4b5441
- [AVR] Fix build after r334078 · 6cfb31c7
  Alex Bradbury authored Jun 07, 2018
  6cfb31c7
- [X86][SSE] Simplify combineVectorTruncationWithPACKUS. NFCI. · 51ff15f4
  Simon Pilgrim authored Jun 07, 2018
  51ff15f4
- [PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector · 01ef4c2c
  Hiroshi Inoue authored Jun 07, 2018
  01ef4c2c
- [Mips] Silencing warnings in instruction info (NFC) · 241f286b
  Petar Jovanovic authored Jun 07, 2018
  241f286b
- [X86][SSE] Simplify combineVectorTruncationWithPACKSS to reduce code duplication · 09953d84
  Simon Pilgrim authored Jun 07, 2018
  09953d84
- [PowerPC] fix trivial typos in comment, NFC · b5578460
  Hiroshi Inoue authored Jun 07, 2018
  b5578460
- AMDGPU: Fix not including v2f64 in SReg_128 · f1c868ef
  Matt Arsenault authored Jun 07, 2018
  f1c868ef
- [Mem2Reg] Avoid replacing load with itself in promoteSingleBlockAlloca. · 0d6b0176
  Florian Hahn authored Jun 07, 2018
  0d6b0176
- AMDGPU: Use scalar operations for f16 fabs/fneg patterns · 697300bd
  Matt Arsenault authored Jun 07, 2018
  697300bd
- AMDGPU: Try a lot harder to emit scalar loads · 90083d30
  Matt Arsenault authored Jun 07, 2018
  90083d30
- [X86][NFC] Fix harmless typo in BtVer2 model. · 4281b1d3
  Clement Courbet authored Jun 07, 2018
  4281b1d3
- [X86] Block UndefRegUpdate · f8c76370
  Tomasz Krupa authored Jun 07, 2018
  f8c76370
- [NFC] Use variable instead of accessing pair many times · b4b2ccea
  Max Kazantsev authored Jun 07, 2018
  b4b2ccea
- Test commit access. · 14582516
  Tomasz Krupa authored Jun 07, 2018
  14582516
- [X86][NFC] Fix harmless typos in BDW/ZnVer1 sched models. · 9212ef0a
  Clement Courbet authored Jun 07, 2018
  9212ef0a
- [BranchFolding] Fix live-in's when hoisting code · abb11f80
  Karl-Johan Karlsson authored Jun 07, 2018
  abb11f80
- [SystemZ] Build Load And Test from scratch in convertToLoadAndTest. · e80d4057
  Jonas Paulsson authored Jun 07, 2018
  e80d4057
- SpeculativeExecution Pass: Set PreserveCFG to avoid unnecessary analyses invalidation. · 31800864
  Michael Zolotukhin authored Jun 07, 2018
  31800864
- [AMDGPU] Improve reciprocal handling · df61be70
  Stanislav Mekhanoshin authored Jun 06, 2018
  df61be70
- [ThinLTO] Rename index IsAnalysis flag to HaveGVs (NFC) · 4ffc3e78
  Teresa Johnson authored Jun 06, 2018
  4ffc3e78
Jun 06, 2018
- [InstCombine] fold another shifty abs pattern to cmp+sel (PR36036) · 3cd1aa88
  Sanjay Patel authored Jun 06, 2018
  3cd1aa88
- AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16 · e9524f1f
  Matt Arsenault authored Jun 06, 2018
  e9524f1f
- [InstCombine] PR37603: low bit mask canonicalization · cbf84463
  Roman Lebedev authored Jun 06, 2018
  cbf84463
- [X86] Emit BZHI when mask is ~(-1 << nbits)) · 488d28d4
  Roman Lebedev authored Jun 06, 2018
  488d28d4
- [Hexagon] Implement vector-pair zero as V6_vsubw_dv · c1e712ba
  Krzysztof Parzyszek authored Jun 06, 2018
  c1e712ba
- [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index. · ef813a52
  Craig Topper authored Jun 06, 2018
  ef813a52
- [X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem. · d04cc8e6
  Craig Topper authored Jun 06, 2018
  d04cc8e6
- [X86][BtVer2] Add support for all vector instructions that should match the... · aef5bdbe
  Simon Pilgrim authored Jun 06, 2018
  aef5bdbe
- [AArch64, ARM] Add support for Samsung Exynos M4 · b2c82447
  Evandro Menezes authored Jun 06, 2018
  b2c82447
- guard fsqrt with fmf sub flags · cc1c4b69
  Michael Berg authored Jun 06, 2018
  cc1c4b69
- [Hexagon] Split CTPOP of vector pairs · 0da1fe37
  Krzysztof Parzyszek authored Jun 06, 2018
  0da1fe37
- Change TII isCopyInstr way of returning arguments(NFC) · 8cb6a521
  Petar Jovanovic authored Jun 06, 2018
  8cb6a521