llvm-svn: 136215

llvm-svn: 136212

Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.

llvm-svn: 136141

llvm-svn: 136090

Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.

llvm-svn: 136027

llvm-svn: 136006

llvm-svn: 135841

Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller.

Goodbye static ctors and dtors!

llvm-svn: 135836

This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.

llvm-svn: 135835

The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823

llvm-svn: 135816

llvm-svn: 135768

- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.

llvm-svn: 135735

Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.

llvm-svn: 135722

Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates.  This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.

llvm-svn: 135693

to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.

llvm-svn: 135669

Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626

llvm-svn: 135524

Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500

Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding.  This resolves another conflict when bringing up the new-style disassembler.

llvm-svn: 135442

to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424

Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414

Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.

ListTy instance pointers are stored in the element RecTy instance.

BitsRecTy instance pointers, one per length, are stored in a static vector.

Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.

This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.

llvm-svn: 135399

Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.

llvm-svn: 135390

llvm-svn: 135343

Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32.  This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb.  Part of PR8873.

llvm-svn: 135337

Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135319

llvm-svn: 135287

MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

llvm-svn: 135269

- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.

llvm-svn: 135197

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

conceptually have nuls in it.

llvm-svn: 135165

llvm-svn: 135154

Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode.  Switch ARM over to using that rather than its own special MCInstrDesc bits.

llvm-svn: 135106

Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

llvm-svn: 135097

llvm-svn: 135092

The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066

in multiple buildbots.

llvm-svn: 134936

Respond to some feedback asking for a name change.

llvm-svn: 134921

llvm-svn: 134917