This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875

llvm-svn: 115874

llvm-svn: 115872

llvm-svn: 115860

Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859

llvm-svn: 115858

llvm-svn: 115857

llvm-svn: 115853

llvm-svn: 115845

"lane" operand modifier.

llvm-svn: 115843

llvm-svn: 115841

pseudo instructions.

llvm-svn: 115840

llvm-svn: 115837

being aliased.

llvm-svn: 115836

llvm-svn: 115835

llvm-svn: 115833

llvm-svn: 115831

llvm-svn: 115830

llvm-svn: 115829

llvm-svn: 115827

rather than being fixed to the global registry.

llvm-svn: 115824

llvm-svn: 115817

llvm-svn: 115802

llvm-svn: 115799

llvm-svn: 115798

llvm-svn: 115795

llvm-svn: 115793

llvm-svn: 115792

llvm-svn: 115788

llvm-svn: 115777

llvm-svn: 115764

fix is trying to accomplish.

This code could still use some polishing.

llvm-svn: 115759

Patch by John Tytgat.

llvm-svn: 115757

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.

The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.

<rdar://problem/8198537>

llvm-svn: 115753

operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752

llvm-svn: 115749

llvm-svn: 115748

that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).

llvm-svn: 115747

llvm-svn: 115745