llvm-svn: 115898

allowing us to convert ADD over.  deletes 160 lines of .td file.

llvm-svn: 115897

Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.

llvm-svn: 115896

which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.

llvm-svn: 115893

llvm-svn: 115890

This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.

llvm-svn: 115885

llvm-svn: 115884

As usual, no change in generated .inc files.

llvm-svn: 115882

Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet.

llvm-svn: 115881

llvm-svn: 115880

instructions.

This unbreaks the machine code verifier and fixes PR8317.

llvm-svn: 115879

convert AND64ri32 to use BinOpRI.

llvm-svn: 115878

This function looks like it is about ready to be generated by TebleGen.

llvm-svn: 115876

This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875

llvm-svn: 115874

llvm-svn: 115860

Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859

llvm-svn: 115858

llvm-svn: 115857

llvm-svn: 115853

llvm-svn: 115845

"lane" operand modifier.

llvm-svn: 115843

pseudo instructions.

llvm-svn: 115840

being aliased.

llvm-svn: 115836

llvm-svn: 115835

llvm-svn: 115833

llvm-svn: 115831

llvm-svn: 115830

llvm-svn: 115827

llvm-svn: 115817

llvm-svn: 115802

llvm-svn: 115798

llvm-svn: 115795

llvm-svn: 115793

llvm-svn: 115792

fix is trying to accomplish.

This code could still use some polishing.

llvm-svn: 115759

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.

The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.

<rdar://problem/8198537>

llvm-svn: 115753

operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752

llvm-svn: 115748