llvm-svn: 115898

allowing us to convert ADD over.  deletes 160 lines of .td file.

llvm-svn: 115897

Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.

llvm-svn: 115896

which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.

llvm-svn: 115893

llvm-svn: 115890

This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.

llvm-svn: 115885

llvm-svn: 115884

As usual, no change in generated .inc files.

llvm-svn: 115882

llvm-svn: 115880

instructions.

This unbreaks the machine code verifier and fixes PR8317.

llvm-svn: 115879

convert AND64ri32 to use BinOpRI.

llvm-svn: 115878

This function looks like it is about ready to be generated by TebleGen.

llvm-svn: 115876

llvm-svn: 115860

Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859

llvm-svn: 115853

llvm-svn: 115845

"lane" operand modifier.

llvm-svn: 115843

pseudo instructions.

llvm-svn: 115840

llvm-svn: 115831

llvm-svn: 115798

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752

llvm-svn: 115748

that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).

llvm-svn: 115747

llvm-svn: 115745

llvm-svn: 115744

gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)

llvm-svn: 115727

that I need a heavier handed approach to get ultimate factorization.

llvm-svn: 115726

where !cast is just as short.

llvm-svn: 115722

  let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720

!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719

llvm-svn: 115717

register class, and use this to simplify use of BinOpRR.

llvm-svn: 115716

llvm-svn: 115715

32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711

convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)

llvm-svn: 115707

(e.g. CMOVBE16rr instead of CMOVBErr16).

llvm-svn: 115705

simplify the X86 CMOVmr's.

llvm-svn: 115702

and verbosity

llvm-svn: 115701

21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.

llvm-svn: 115697