llvm-svn: 148408

llvm-svn: 148401

llvm-svn: 148400

llvm-svn: 148384

Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted.

llvm-svn: 148383

Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE

llvm-svn: 148377

Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.

rdar://10348687.

llvm-svn: 148366

llvm-svn: 148364

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363

Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357

The JIT is expected to take ownership of the TM that's passed in. The MCJIT
wasn't freeing it, resulting in leaks.

llvm-svn: 148356

Add a trivial implementation of the getCallPreservedMask() hook.

llvm-svn: 148347

llvm-svn: 148342

When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687

llvm-svn: 148341

llvm-svn: 148338

llvm-svn: 148337

llvm-svn: 148334

autorelease push+pop pairs.

llvm-svn: 148330

EP_ModuleOptimizerEarly, to allow passes to be added before the
main ModulePass optimizers.

llvm-svn: 148329

llvm-svn: 148322

llvm-svn: 148321

llvm-svn: 148312

Instead, we now put the attributes of the container into members.

llvm-svn: 148302

llvm-svn: 148301

In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.

llvm-svn: 148298

llvm-svn: 148297

llvm-svn: 148295

llvm-svn: 148293

llvm-svn: 148291

Responding to code review.

llvm-svn: 148290

More short term hackery until we have a way to configure passes that work on LiveIntervals.

llvm-svn: 148289

It's becoming clear that LoopSimplify needs to unconditionally create loop preheaders. But that is a bigger fix. For now, continuing to hack LSR.
Fixes rdar://10701050 "Cannot split an edge from an IndirectBrInst" assert.

llvm-svn: 148288

Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.

llvm-svn: 148285

llvm-svn: 148284

or clang bootstrap.

I will keep an eye on the bots.

Original message:
Only emit the Leh_func_endN symbol when needed.

llvm-svn: 148283

Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get checked for legalisation

llvm-svn: 148275

llvm-svn: 148268

llvm-svn: 148265

llvm-svn: 148264

llvm-svn: 148263