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  1. Sep 12, 2012
  2. Sep 06, 2012
  3. Aug 22, 2012
  4. Jun 09, 2012
    • Jakob Stoklund Olesen's avatar
      Also compute MBB live-in lists in the new rewriter pass. · be336295
      Jakob Stoklund Olesen authored
      This deduplicates some code from the optimizing register allocators, and
      it means that it is now possible to change the register allocators'
      solutions simply by editing the VirtRegMap between the register
      allocator pass and the rewriter.
      
      llvm-svn: 158249
      be336295
    • Jakob Stoklund Olesen's avatar
      Reintroduce VirtRegRewriter. · 1224312f
      Jakob Stoklund Olesen authored
      OK, not really. We don't want to reintroduce the old rewriter hacks.
      
      This patch extracts virtual register rewriting as a separate pass that
      runs after the register allocator. This is possible now that
      CodeGen/Passes.cpp can configure the full optimizing register allocator
      pipeline.
      
      The rewriter pass uses register assignments in VirtRegMap to rewrite
      virtual registers to physical registers, and it inserts kill flags based
      on live intervals.
      
      These finalization steps are the same for the optimizing register
      allocators: RABasic, RAGreedy, and PBQP.
      
      llvm-svn: 158244
      1224312f
  5. Feb 17, 2012
    • Jakob Stoklund Olesen's avatar
      Transfer regmasks to MRI. · a0cf42f2
      Jakob Stoklund Olesen authored
      MRI keeps track of which physregs have been used. Make sure it gets
      updated with all the regmask-clobbered registers.
      
      Delete the closePhysRegsUsed() function which isn't necessary.
      
      llvm-svn: 150830
      a0cf42f2
  6. Jan 19, 2012
  7. Jan 07, 2012
  8. Jan 03, 2012
  9. Nov 13, 2011
  10. Oct 05, 2011
    • Jakob Stoklund Olesen's avatar
      Also add <imp-use,kill> flags for redefined super-registers. · d5d39bb0
      Jakob Stoklund Olesen authored
      For example:
      
        %vreg10:dsub_0<def,undef> = COPY %vreg1
        %vreg10:dsub_1<def> = COPY %vreg2
      
      is rewritten as:
      
        %D2<def> = COPY %D0, %Q1<imp-def>
        %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def>
      
      The first COPY doesn't care about the previous value of %Q1, so it
      doesn't read that register.
      
      The second COPY is a partial redefinition of %Q1, so it implicitly kills
      and redefines that register.
      
      This makes it possible to recognize instructions that can harmlessly
      clobber the full super-register.  The write and don't read the
      super-register.
      
      llvm-svn: 141139
      d5d39bb0
  11. Sep 15, 2011
  12. May 06, 2011
  13. Apr 27, 2011
  14. Mar 31, 2011
  15. Mar 23, 2011
  16. Feb 18, 2011
  17. Jan 10, 2011
  18. Jan 09, 2011
  19. Nov 16, 2010
  20. Oct 08, 2010
  21. Jul 22, 2010
  22. Feb 26, 2010
    • Jakob Stoklund Olesen's avatar
      Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl(). · ddbf7a85
      Jakob Stoklund Olesen authored
      The PowerPC floating point registers can represent both f32 and f64 via the
      two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
      allow cross-class coalescing. This coalescing only affects whether registers
      are spilled as f32 or f64.
      
      Spill slots must be accessed with load/store instructions corresponding to the
      class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
      at the instruction opcode which is wrong.
      
      X86 has similar floating point register classes, but doesn't try to fold
      memory operands, so there is no problem there.
      
      llvm-svn: 97262
      ddbf7a85
  23. Feb 10, 2010
  24. Jan 05, 2010
  25. Nov 12, 2009
    • David Greene's avatar
      · 1fbe0544
      David Greene authored
      Add a bool flag to StackObjects telling whether they reference spill
      slots.  The AsmPrinter will use this information to determine whether to
      print a spill/reload comment.
      
      Remove default argument values.  It's too easy to pass a wrong argument
      value when multiple arguments have default values.  Make everything
      explicit to trap bugs early.
      
      Update all targets to adhere to the new interfaces..
      
      llvm-svn: 87022
      1fbe0544
  26. Nov 04, 2009
    • Lang Hames's avatar
      The Indexes Patch. · 05fb9637
      Lang Hames authored
      This introduces a new pass, SlotIndexes, which is responsible for numbering
      instructions for register allocation (and other clients). SlotIndexes numbering
      is designed to match the existing scheme, so this patch should not cause any
      changes in the generated code.
      
      For consistency, and to avoid naming confusion, LiveIndex has been renamed
      SlotIndex.
      
      The processImplicitDefs method of the LiveIntervals analysis has been moved
      into its own pass so that it can be run prior to SlotIndexes. This was
      necessary to match the existing numbering scheme.
      
      llvm-svn: 85979
      05fb9637
  27. Oct 17, 2009
  28. Aug 23, 2009
  29. Jul 24, 2009
  30. Jun 15, 2009
    • Evan Cheng's avatar
      Part 1. · 1283c6a0
      Evan Cheng authored
      - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
      - Allow targets to specify alternative register allocation orders based on allocation hint.
      
      Part 2.
      - Use the register allocation hint system to implement more aggressive load / store multiple formation.
      - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
      v1025 = LDR v1024, 0
      v1026 = LDR v1024, 0
      =>
      v1025,v1026 = LDRD v1024, 0
      
      If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
      
      - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
      
      This is work in progress, not yet enabled.
      
      llvm-svn: 73381
      1283c6a0
  31. Jun 14, 2009
  32. May 04, 2009
  33. May 03, 2009
    • Evan Cheng's avatar
      In some rare cases, the register allocator can spill registers but end up not... · 210fc62a
      Evan Cheng authored
      In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However,  reloads and restores might be folded into uses / defs and freed registers might not be used at all.
      
      VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
      
      Not yet enabled. This is part 1. More coming.
      
      llvm-svn: 70787
      210fc62a
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