llvm-svn: 57845

llvm-svn: 57844

result type when the result type is legal but
not the operand type.  Add additional support
for EXTRACT_SUBVECTOR and CONCAT_VECTORS,
needed to handle such cases.

llvm-svn: 57840

llvm-svn: 57838

with TLI.getPointerTy for a small simplification.

llvm-svn: 57837

the condition of a SELECT node.  Make sure that the
correct extension type (any-, sign- or zero-extend)
is used.

llvm-svn: 57836

llvm-svn: 57834

use an MVT::i1 and simplify the code while there.

llvm-svn: 57833

LowerOperation if it doesn't know what else to do.
This methods should probably be factorized some,
but this is good enough for the moment.  Have
LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather
than assuming the operand is a BUILD_PAIR (if it
is then getNode will automagically simplify the
EXTRACT_ELEMENT).  This way LowerATOMIC_BINARY_64
usable from LegalizeTypes.

llvm-svn: 57831

be either deleted or referenced afterwards.

llvm-svn: 57786

llvm-svn: 57785

this everywhere in LegalizeTypes.

llvm-svn: 57783

elements.  Otherwise LegalizeTypes will, reasonably
enough, legalize the mask, which may result in it
no longer being a BUILD_VECTOR node (LegalizeDAG
simply ignores the legality or not of vector masks).

llvm-svn: 57782

the previous patch this one actually passes make check.

"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."

llvm-svn: 57771

llvm-svn: 57770

llvm-svn: 57766

llvm-svn: 57765

and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.

llvm-svn: 57747

llvm-svn: 57734

llvm-svn: 57733

ISD condition opcodes into helper functions.

llvm-svn: 57726

Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.

llvm-svn: 57723

Patch by Lang Hames!

llvm-svn: 57720

llvm-svn: 57715

have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714

touches memory and need an associated MemOperand

llvm-svn: 57712

ISD condition opcodes into helper functions.

llvm-svn: 57710

llvm-svn: 57709

in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.

llvm-svn: 57704

that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.

llvm-svn: 57699

Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.

llvm-svn: 57692

llvm-svn: 57691

llvm-svn: 57690

constraint.  Reject asms where an output has multiple
input constraints tied to it.

llvm-svn: 57687

array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.

llvm-svn: 57686

llvm-svn: 57673

should work for intel long double, but ppc long double aborts
in convert.

llvm-svn: 57672

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662