As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.

llvm-svn: 191520

This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519

This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518

No functional change.

llvm-svn: 191517

llvm-svn: 191516

For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515

For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514

llvm-svn: 191513

llvm-svn: 191512

Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511

[asan] introduce run-time flag uar_stack_size_log to control the size of FakeStack; don't crash when the fake stack is exhausted, move some code to .cc file

llvm-svn: 191510

This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.

llvm-svn: 191509

Fixes PR17377.

llvm-svn: 191508

This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.

llvm-svn: 191507

llvm-svn: 191506

llvm-svn: 191505

ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.

LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.

llvm-svn: 191504

lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.

lowerMSASplat now takes its callers SDLoc instead of making a new one.

No functional change.

llvm-svn: 191503

llvm-svn: 191500

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

llvm-svn: 191498

Summary:
The width of the first inserted tab character depends on the initial
column, so we need to handle the first tab in a special manner.

Reviewers: klimek, djasper

Reviewed By: klimek

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1763

llvm-svn: 191497

llvm-svn: 191496

Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495

Before:
  void SomeFunction(aaaaaaaaaaaaaaaaaaaaaaaaaa,
                    aaaaaaaaaaaaaaaaaaaaaaaaaa) override
  final;

After:
  void SomeFunction(aaaaaaaaaaaaaaaaaaaaaaaaaa,
                    aaaaaaaaaaaaaaaaaaaaaaaaaa) override final;

llvm-svn: 191494

We previously handled one-dimensional arrays but didn't consider the
general case.  The fix is simple: keep going through subsequent
dimensions until we get to the base element.

llvm-svn: 191493

Before:
  template <typename T>
  // T should be one of {A, B}.
      void f() {}

After:
  template <typename T>
  // T should be one of {A, B}.
  void f() {}

llvm-svn: 191492

llvm-svn: 191491

Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.

llvm-svn: 191490

llvm-svn: 191489

llvm-svn: 191488

The intent of getTypeOperand() was to yield an unqualified type.
However QualType::getUnqualifiedType() does not strip away qualifiers on
arrays.

N.B.  This worked fine when typeid() was applied to an expression
because we would inject as implicit cast to the unqualified array type
in the AST.

llvm-svn: 191487

both flags to the driver test.

llvm-svn: 191486

Investigating yet. It seems msc16 miscompiles s[1] to be folded.

llvm-svn: 191485

Functions declared as constexpr must have their parsing delayed in
-fdelayed-template-parsing mode so as not to upset later template
instantiation.

N.B. My reading of the standard makes it seem like delayed template
parsing is at odds with constexpr.  We may want to make refinements in
other places in clang to make constexpr play nicer with this feature.

This fixes PR17334.

llvm-svn: 191484

Remove some stray underscores from copyright block. Fix first line length to match length of the one after the copyright block.

llvm-svn: 191483

Fixes https://code.google.com/p/thread-sanitizer/issues/detail?id=29

llvm-svn: 191482

Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481

This reverts commit r191472 because it's failing on BE machine.

llvm-svn: 191480

This reverts r191469 because the original patch this one depends on (r191472)
was reverted.

llvm-svn: 191479

line breakpoints past the prologue of functions so it can be shared between the
file & line breakpoint resolver, and the source pattern breakpoint resolver,
and then share it.

llvm-svn: 191478