vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27412

llvm-svn: 27410

llvm-svn: 27405

llvm-svn: 27393

llvm-svn: 27388

llvm-svn: 27384

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

llvm-svn: 27310

from a 128-bit vector.

llvm-svn: 27304

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

llvm-svn: 27257

llvm-svn: 27256

llvm-svn: 27255

For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250

integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248

- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

- Other shuffle related fixes.

llvm-svn: 27244

The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240

llvm-svn: 27221

llvm-svn: 27219

* Bug fixes.

llvm-svn: 27218

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27174

llvm-svn: 27167

llvm-svn: 27150

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27103

llvm-svn: 27096

llvm-svn: 27094

llvm-svn: 27091

llvm-svn: 27087

llvm-svn: 27083

llvm-svn: 27056

llvm-svn: 27040