Commits · 1cf75767079d6287e71ffa0b750a94c907b700c5 · Roger Ferrer / llvm-epi-0.8

Dec 24, 2011
- Add MachineMemOperands to instructions generated in storeRegToStackSlot or · 1cf75767
  Akira Hatanaka authored Dec 24, 2011
```
loadRegFromStackSlot. 

llvm-svn: 147235
```
  1cf75767
Dec 19, 2011
- Tidy up. Simplify logic. No functional change intended. · 9e1d369e
  Akira Hatanaka authored Dec 19, 2011
```
llvm-svn: 146896
```
  9e1d369e
Dec 12, 2011
- Emit B (unconditional branch) when -relocation-model=pic and J (jump) when · 5d5e0d81
  Akira Hatanaka authored Dec 12, 2011
```
-relocation-model=static.

llvm-svn: 146432
```
  5d5e0d81
Dec 06, 2011
- Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter · 0c24d8a4
  Bruno Cardoso Lopes authored Dec 06, 2011
```
llvm-svn: 145912
```
  0c24d8a4
Nov 07, 2011
- Add code needed for copying between 64-bit integer and floating pointer · 81c14002
  Akira Hatanaka authored Nov 07, 2011
```
registers.

llvm-svn: 144017
```
  81c14002
Oct 11, 2011
- Add support for conditional branch instructions with 64-bit register operands. · 4b6ac98f
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141694
```
  4b6ac98f
- Make changes necessary for supporting floating point load and store instructions · b6d72cbe
  Akira Hatanaka authored Oct 11, 2011
```
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
```
  b6d72cbe
- Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. · e6ced5b3
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141613
```
  e6ced5b3
Oct 08, 2011
- Simplify definition of FP move instructions. · 6be7d6c9
  Akira Hatanaka authored Oct 08, 2011
```
llvm-svn: 141476
```
  6be7d6c9
Oct 03, 2011
- Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer · 3caf8cb3
  Akira Hatanaka authored Oct 03, 2011
```
registers.

llvm-svn: 141019
```
  3caf8cb3
Sep 29, 2011
- Revert r140731, "Define classes for unary and binary FP instructions and use them to define" · 67289582
  Jakob Stoklund Olesen authored Sep 28, 2011
```
It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735
```
  67289582
Sep 28, 2011
- Define classes for unary and binary FP instructions and use them to define · 5a1b4a80
  Akira Hatanaka authored Sep 28, 2011
```
multiclasses.

llvm-svn: 140731
```
  5a1b4a80
Aug 24, 2011
- Move TargetRegistry and TargetSelect from Target to Support where they belong. · 2bb40357
  Evan Cheng authored Aug 24, 2011
```
These are strictly utilities for registering targets and components.

llvm-svn: 138450
```
  2bb40357
Aug 16, 2011

Fix handling of double precision loads and stores when Mips1 is targeted. · 2263c109

Akira Hatanaka authored Aug 16, 2011

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

2263c109

Jul 14, 2011
- Next round of MC refactoring. This patch factor MC table instantiations, MC · bc153d49
  Evan Cheng authored Jul 14, 2011
```
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
```
  bc153d49
Jul 11, 2011

- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo · c5e6d2f5

Evan Cheng authored Jul 11, 2011

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

c5e6d2f5

Jul 08, 2011
- Lower MachineInstr to MC Inst and print to .s files. · 9c6028f9
  Akira Hatanaka authored Jul 07, 2011
```
llvm-svn: 134661
```
  9c6028f9
Jul 07, 2011
- Reverse order of operands of address operand mem so that the base operand comes · 2e766ed2
  Akira Hatanaka authored Jul 07, 2011
```
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
```
  2e766ed2
Jul 01, 2011
- Hide the call to InitMCInstrInfo into tblgen generated ctor. · 703a0fbf
  Evan Cheng authored Jul 01, 2011
```
llvm-svn: 134244
```
  703a0fbf
- Improve Mips back-end's handling of DBG_VALUE. · f2bcad97
  Akira Hatanaka authored Jul 01, 2011
```
llvm-svn: 134224
```
  f2bcad97
Jun 28, 2011
- Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. · 194c3dc0
  Evan Cheng authored Jun 28, 2011
```
llvm-svn: 134030
```
  194c3dc0
- Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc · 1e210d08
  Evan Cheng authored Jun 28, 2011
```
llvm-svn: 134024
```
  1e210d08
- - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and · 6cc775f9
  Evan Cheng authored Jun 28, 2011
```
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
```
  6cc775f9
Apr 15, 2011
- Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. · e2489125
  Akira Hatanaka authored Apr 15, 2011
```
llvm-svn: 129612
```
  e2489125
- Fix lines that have incorrect indentation or exceed 80 columns. There is no... · aef55c88
  Akira Hatanaka authored Apr 15, 2011
```
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606
```
  aef55c88
Apr 01, 2011
- Add code for analyzing FP branches. Clean up branch Analysis functions. · 93f898f6
  Akira Hatanaka authored Apr 01, 2011
```
llvm-svn: 128718
```
  93f898f6
Mar 31, 2011
- Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. · a535270d
  Akira Hatanaka authored Mar 31, 2011
```
llvm-svn: 128650
```
  a535270d
Mar 04, 2011
- Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira · ed874eff
  Bruno Cardoso Lopes authored Mar 04, 2011
```
llvm-svn: 127003
```
  ed874eff
Jul 17, 2010
- Remove the isMoveInstr() hook. · 8289f785
  Jakob Stoklund Olesen authored Jul 16, 2010
```
llvm-svn: 108567
```
  8289f785
Jul 11, 2010
- RISC architectures get their memory operand folding for free. · 0961c551
  Jakob Stoklund Olesen authored Jul 11, 2010
```
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099
```
  0961c551
- Replace copyRegToReg with copyPhysReg for Mips. · 7002c314
  Jakob Stoklund Olesen authored Jul 11, 2010
```
llvm-svn: 108066
```
  7002c314
- Use COPY in targets · 60af0681
  Jakob Stoklund Olesen authored Jul 10, 2010
```
llvm-svn: 108063
```
  60af0681
Jun 18, 2010

Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This · 0125b641

Stuart Hastings authored Jun 17, 2010

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

0125b641

May 06, 2010
- Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it · 779c69bb
  Dan Gohman authored May 06, 2010
```
doesn't have to guess.

llvm-svn: 103194
```
  779c69bb
- Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. · efb126a6
  Evan Cheng authored May 06, 2010
```
llvm-svn: 103193
```
  efb126a6
May 05, 2010
- No-ops emitted for scheduling don't correspond with anything in the · f62cd20b
  Dan Gohman authored May 05, 2010
```
user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121
```
  f62cd20b
Apr 02, 2010
- use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() · 6f306d7d
  Chris Lattner authored Apr 02, 2010
```
llvm-svn: 100214
```
  6f306d7d
- Teach AnalyzeBranch, RemoveBranch and the branch · 4244d127
  Dale Johannesen authored Apr 02, 2010
```
folder to be tolerant of debug info following the
branch(es) at the end of a block.

llvm-svn: 100168
```
  4244d127
Jan 19, 2010
- load f64 +0.0 in a cleaner way. This fix part of PR5445 · c9818a77
  Bruno Cardoso Lopes authored Jan 19, 2010
```
llvm-svn: 93876
```
  c9818a77
Dec 05, 2009
- Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of · 047a767d
  Dan Gohman authored Dec 05, 2009
```
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634
```
  047a767d