operands.

llvm-svn: 187238

llvm-svn: 187234

to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233

needed. The generic method printOperand will do.

No functionality change.

llvm-svn: 187231

instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229

when there wasn't a match. This behavior is consistent with other register
parsing methods.

llvm-svn: 187063

Testing commit access credentials.

llvm-svn: 187032

This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.

llvm-svn: 187026

Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861

the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855

No functionality change.

llvm-svn: 186642

This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

llvm-svn: 186567

llvm-svn: 186528

This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions.

llvm-svn: 186512

llvm-svn: 186507

llvm-svn: 186429

llvm-svn: 186403

 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.

llvm-svn: 186397

llvm-svn: 186274

llvm-svn: 186227

llvm-svn: 186222

llvm-svn: 186151

llvm-svn: 186000

llvm-svn: 185999

These exception-related opcodes are not used any longer.

llvm-svn: 185625

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185606

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600

These exception-related opcodes are not used any longer.

llvm-svn: 185596

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185540

floating point loads and stores.

No changes in functionality.

llvm-svn: 185399

have three register operands.

No intended functionality changes.

llvm-svn: 185376

Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373

function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026

llvm-svn: 185012

subs.

llvm-svn: 185011

 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

llvm-svn: 184716

llvm-svn: 184642

llvm-svn: 184411

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

llvm-svn: 184360

The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp

llvm-svn: 184292