For more information, see the accompanying clang patch.

llvm-svn: 111454

and optional def operands are handled in the backend support.

llvm-svn: 111220

instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168

llvm-svn: 111094

Apparently, this is now fixed in Clang.

llvm-svn: 111032

llvm-svn: 111007

Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.

llvm-svn: 110998

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

llvm-svn: 110789

llvm-svn: 110779

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110748

useful after all.

llvm-svn: 110531

Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

llvm-svn: 110446

need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h

llvm-svn: 110424

llvm-svn: 110422

llvm-svn: 110419

to IntrReadWriteArgMem, as it's for reading as well as writing.

llvm-svn: 110395

later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.

llvm-svn: 109901

have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499

llvm-svn: 109842

llvm-svn: 109605

llvm-svn: 109572

Also fix some comments.

llvm-svn: 109499

llvm-svn: 109407

llvmc can be now compiled with llvm-gcc on Windows.

llvm-svn: 109215

llvm-svn: 109043

llvm-svn: 108893

llvm-svn: 108769

llvm-svn: 108718

llvm-svn: 108714

TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
 - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677

llvm-svn: 108673

llvm-svn: 108571

thus is a much more meaningful name.

llvm-svn: 108563

llvm-svn: 108130

llvm-svn: 108071

 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039

notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996