This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.

llvm-svn: 68552

When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.

llvm-svn: 68066

add a fixme note on how to remove code duplication.

llvm-svn: 66932

llvm-svn: 66922

Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative.

llvm-svn: 66803

assembly text output uses an indirect call ("call *") instead of a direct call.

llvm-svn: 66735

llvm-svn: 66725

INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.

llvm-svn: 66207

llvm-svn: 66058

llvm-svn: 66024

llvm-svn: 66008

result from add, sub, inc, and dec instructions in simple cases.

llvm-svn: 66004

instructions. These aren't used yet.

llvm-svn: 65965

llvm-svn: 63852

llvm-svn: 63090

other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980

unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661

to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194

llvm-svn: 62180

llvm-svn: 62179

into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842

llvm-svn: 61836

X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835

Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.

llvm-svn: 61557

llvm-svn: 61425

llvm-svn: 61424

llvm-svn: 61400

  which are identical to the original patterns.

- Change the multiply with overflow so that we distinguish between signed and
  unsigned multiplication. Currently, unsigned multiplication with overflow
  isn't working!

llvm-svn: 60963

ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.

llvm-svn: 60915

target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!

llvm-svn: 60800

llvm-svn: 60651

llvm-svn: 60487

llvm-svn: 60385

llvm-svn: 60383

- Add support for seto, setno, setc, and setnc instructions.

llvm-svn: 60382

the conditional for the BRCOND statement. For instance, it will generate:

    addl %eax, %ecx
    jo LOF

instead of

    addl %eax, %ecx
    ; About 10 instructions to compare the signs of LHS, RHS, and sum.
    jl LOF

llvm-svn: 60123

they trap on divide-by-zero, and this side effect is otherwise
unmodeled.

llvm-svn: 59551

llvm-svn: 58141

Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.

llvm-svn: 57723

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663