llvm-svn: 76646

llvm-svn: 76645

llvm-svn: 76639

llvm-svn: 76635

llvm-svn: 76634

be useful, and it's currently unused.  (Some issues: it isn't actually 
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)

llvm-svn: 76633

llvm-svn: 76631

Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

llvm-svn: 76612

and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604

Add PrefixPrinter arguments to the dump routines for MachineFunction and
MachineBasicBlock.  We'll use these shortly.

llvm-svn: 76603

llvm-svn: 76600

llvm-svn: 76598

llvm-svn: 76596

llvm-svn: 76595

chain to the super class instead of initializing mangler directly.
This gives it .file and module level inline asm support among other
things.

llvm-svn: 76593

This eliminates redundancy setting up the mangler and adds support to them
for module-level inline asm and a .file directive.

llvm-svn: 76592

LLVM IR concept.

llvm-svn: 76590

llvm-svn: 76587

llvm-svn: 76586

vectors needlessly, doxygenify comments, improve constness, etc.

llvm-svn: 76585

as much, etc.

llvm-svn: 76578

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

llvm-svn: 76558

llvm-svn: 76555

llvm-svn: 76554

llvm-svn: 76553

llvm-svn: 76541

global declared symbols are initialized with references from other global
symbols.

llvm-svn: 76540

llvm-svn: 76536

Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or                                                                              
                              (srl (and x, (shl -1, c1)), (sub c1, c2))

llvm-svn: 76535

llvm-svn: 76533

- SYSCALL (normal fast system call instruction) [0f 05]
- SYSENTER (system call entry instruction) [0f 34]
- SYSEXIT (system call exit instruction) [0f 35]
- SYSEXIT64 (system call exit instruction to 64-bit user code) [REX.W 0f 35]
- SYSRET (system call return instruction) [0f 07]

Patch by Sean Callanan.

llvm-svn: 76528

as they aren't currently prepared to handle complicated overflow
cases.

llvm-svn: 76524

llvm-svn: 76523

llvm-svn: 76521

llvm-svn: 76520

llvm-svn: 76519

llvm-svn: 76517

llvm-svn: 76505

by determining if (B pred (B-A)) is known, as it doesn't handle
overflow correctly.

llvm-svn: 76504