"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.

this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!

llvm-svn: 100875

llvm-svn: 97814

Default HasSetDirective to true, since most targets have it.

The targets that claim to not have it probably do, or it is
spelled differently. These include Blackfin, Mips, Alpha, and
PIC16.  All of these except pic16 are normal ELF targets, so
they almost certainly have it.

llvm-svn: 94585

that has it.

llvm-svn: 94581

llvm-svn: 94299

stomache MCAsmInfo having this, and I found a better solution to
this layering issue.

llvm-svn: 93985

I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.

I may change this in the future, we'll see how it works out.

llvm-svn: 93934

llvm-svn: 79763

pair instead of from a virtual method on TargetMachine.  This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use 
TargetAsmInfo.

llvm-svn: 78802

"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.

llvm-svn: 78737

and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625

TLOF, unifying all the dwarf targets at the same time.

llvm-svn: 77889

llvm-svn: 77869

no longer depends on TM!

llvm-svn: 77863

llvm-svn: 77820

llvm-svn: 77723

it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.

Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.

This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
   pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
   CStringSection_.  Factor the code better.
5. fixes some bugs in string lowering on ELF targets.

llvm-svn: 77294

instead.

llvm-svn: 77186

instead and drive things based off of that.

llvm-svn: 77184

'unnamed' bss section, but some impls would want a named one.  Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.

llvm-svn: 77165

1. Spell SectionFlags::Writeable as "Writable".
2. Add predicates for deriving SectionFlags from SectionKinds.
3. Sink ELF-specific getSectionPrefixForUniqueGlobal impl into
   ELFTargetAsmInfo.
4. Fix SectionFlagsForGlobal to know that BSS/ThreadBSS has the
   BSS bit set (the real fix for PR4619).
5. Fix isSuitableForBSS to not put globals with explicit sections
   set in BSS (which was the reason #4 wasn't fixed earlier).
6. Remove my previous hack for PR4619.

llvm-svn: 77085

llvm-svn: 73736

- Update DWARF debugging support.

llvm-svn: 63059

  DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.

llvm-svn: 61447

structure. Assembly printer now outputs the correct section for strings.

llvm-svn: 58921

llvm-svn: 58839

NB: This is likely to need more work.
llvm-svn: 58832

adding a TargetMachine member to the base TargetAsmInfo class instead.

llvm-svn: 58624

llvm-svn: 56580

only two addressing mode nodes, SPUaform and SPUindirect (vice the
three previous ones, SPUaform, SPUdform and SPUxform). This improves
code somewhat because we now avoid using reg+reg addressing when
it can be avoided. It also simplifies the address selection logic,
which was the main point for doing this.

Also, for various global variables that would be loaded using SPU's
A-form addressing, prefer D-form offs[reg] addressing, keeping the
base in a register if the variable is used more than once.

llvm-svn: 46483

llvm-svn: 45418

llvm-svn: 44597

remain.

llvm-svn: 44595