llvm-svn: 93590

replace it.  Upgrade Alpha, Blackfin, and part of CellSPU to not
use mangler anymore.  CellSPU needs more invasive surgery.

llvm-svn: 93589

llvm-svn: 93587

llvm-svn: 93582

llvm-svn: 93580

llvm-svn: 93578

Fix PR6019.  A load has more than one use if it feeds a bitconvert that
has more than one use.

llvm-svn: 93576

helper method, use it to simplify some code.

llvm-svn: 93575

llvm-svn: 93570

target-dependent memory address representation in it.
Restore X86 printing of DEBUG_VALUE; lowering is
done in X86RegisterInfo using the normal algorithm.

llvm-svn: 93565

handle physical registers R0-R7 when described as having a non-tGPR register
class.

llvm-svn: 93564

llvm-svn: 93563

users.

llvm-svn: 93558

llvm-svn: 93556

llvm-svn: 93554

llvm-svn: 93553

llvm-svn: 93552

Add micro-optimization which allows us to fold imm into cmp. This allows us to save 1 word (sometimes) and reduce register pressure.

llvm-svn: 93551

llvm-svn: 93550

unneeded argument from ParseExpression.

llvm-svn: 93536

X86Operand's have range info.

llvm-svn: 93535

to return range information for subexpressions.  Use this to
provide range info for several new X86Operands.

llvm-svn: 93534

llvm-svn: 93532

FrameIndexes should be lowered, but the same way as
everything else (target dependent) rather than in a
special hacked way.  The lowering needs to be done
for eventual purposes of Dwarf generation.

llvm-svn: 93530

X86Operand::Create* implementations to avoid
copy ctor use.

llvm-svn: 93528

llvm-svn: 93526

datastructure when parsing a mem operand.

llvm-svn: 93521

print it as a comment on X86.

llvm-svn: 93499

"icmp lhs, rhs" into "cmp rhs, lhs". This should fix PR5979.

llvm-svn: 93496

llvm-svn: 93480

EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this.

llvm-svn: 93479

JITTest.FunctionIsRecompiledAndRelinked.)

llvm-svn: 93475

the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471

the new ParseInstruction method just parses and returns a list of
target operands.  A new MatchInstruction interface is used to
turn the operand list into an MCInst.

This requires new/deleting all the operands, but it also gives 
targets the ability to use polymorphic operands if they want to. 

llvm-svn: 93469

llvm-svn: 93467

Pass in SMLoc of instr opcode into ParseInstruction.
Make AsmToken be a class, not a struct.

llvm-svn: 93457

llvm-svn: 93455

llvm-svn: 93454

This is consistent with llvm-gcc's arm/constraints.md.

Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.

llvm-svn: 93436

An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

llvm-svn: 93393