We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

llvm-svn: 151571

to make it more widely available.

llvm-svn: 151564

Teach BasicAA about the LLVM IR rules that allow reading past the end of an object given sufficient alignment.  Fixes PR12098.

llvm-svn: 151553

llvm-svn: 151552

http://llvm.org/bugs/show_bug.cgi?id=12089

llvm-svn: 151550

MCize function entry label emission on PowerPC64 properly.

llvm-svn: 151547

rdar://10921670
PR11935

llvm-svn: 151543

llvm-svn: 151540

llvm-svn: 151538

After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

llvm-svn: 151531

thumb instruction.  The PC adjustment is +4 in Thumb mode and +8 in ARM mode.

llvm-svn: 151530

The MIOperands iterator can visit operands on a single instruction, or
all operands in a bundle.  This simplifies code like the register
allocator that treats bundles as a set of operands.

llvm-svn: 151529

Found by valgrind.

llvm-svn: 151525

llvm-svn: 151524

where sizeof (T) is a multiple of 4.

llvm-svn: 151523

value numbers to be assigned when calculating any particular value number.
Enhance the logic that detects new value numbers to take this into account,
for a tiny compile time speedup.  Fix a comment typo while there.

llvm-svn: 151522

%cmp (eg: A==B) we already replace %cmp with "true" under the true edge, and
with "false" under the false edge.  This change enhances this to replace the
negated compare (A!=B) with "false" under the true edge and "true" under the
false edge.  Reported to improve perlbench results by 1%.

llvm-svn: 151517

Remove HexagonGenIntrinsics.inc from Hexagon cmake file. It does not appear in the Makefile and the output it produces isn't used. The Hexagon intrinsics are all in the global Intrinsics.gen.

llvm-svn: 151514

llvm-svn: 151513

llvm-svn: 151512

properties (invoke). Just assert that the instruction we return dominates
the insertion point.

llvm-svn: 151511

llvm-svn: 151510

llvm-svn: 151507

llvm-svn: 151506

llvm-svn: 151505

llvm-svn: 151503

llvm-svn: 151502

Patch by Joey Gouly.

llvm-svn: 151489

llvm-svn: 151488

llvm-svn: 151487

Thanks zygoloid.

llvm-svn: 151481

llvm-svn: 151480

Add a random .LL file generator to stress-test different llvm components.

llvm-svn: 151479

llvm-svn: 151475

build. Testcase is still reducing.

llvm-svn: 151474

llvm-svn: 151473

llvm-svn: 151472

llvm-svn: 151471

llvm-svn: 151470

verifier does. This correctly handles invoke.
Thanks to Duncan, Andrew and Chris for the comments.
Thanks to Joerg for the early testing.

llvm-svn: 151469