Commits · 20d73c6cc0e0010edd5e3239b78225388380f0d6 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jul 22, 2015
- [BranchFolding] do not iterate the aliases of virtual registers · 20d73c6c
  Jingyue Wu authored Jul 22, 2015
  20d73c6c
- MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset. · f4baeb51
  Alex Lorenz authored Jul 21, 2015
  f4baeb51
Jul 21, 2015
- [PPC64LE] More vector swap optimization TLC · 2be8054b
  Bill Schmidt authored Jul 21, 2015
  2be8054b
- MIR Serialization: Serialize the external symbol machine operands. · 6ede3744
  Alex Lorenz authored Jul 21, 2015
  6ede3744
- AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , · f7fd547e
  Igor Breger authored Jul 21, 2015
  f7fd547e
- [ARM] Define subtarget feature "reserve-r9", which is used to decide · 28581525
  Akira Hatanaka authored Jul 21, 2015
  28581525
- ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code · a50d2203
  Matthias Braun authored Jul 21, 2015
  a50d2203
- ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 · e40d89ef
  Matthias Braun authored Jul 21, 2015
  e40d89ef
- Revert r242737. · 42427d2c
  Akira Hatanaka authored Jul 20, 2015
  42427d2c
- [ARM] Define subtarget feature "reserve-r9", which is used to decide · 7482d40c
  Akira Hatanaka authored Jul 20, 2015
  7482d40c
- Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2" · 731e359e
  Matthias Braun authored Jul 20, 2015
  731e359e
- Revert "ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code" · 84e28970
  Matthias Braun authored Jul 20, 2015
  84e28970
- Targets: commonize some stack realignment code · e4d22d59
  JF Bastien authored Jul 20, 2015
  e4d22d59
- AArch64: Add aditional Cyclone macroop fusion opportunities · e536f4f6
  Matthias Braun authored Jul 20, 2015
  e536f4f6
- MachineScheduler: Restrict macroop fusion to data-dependent instructions. · 2bd6dd8d
  Matthias Braun authored Jul 20, 2015
  2bd6dd8d
Jul 20, 2015
- [ARM] Refactor the prologue/epilogue emission to be more robust. · 71a71485
  Quentin Colombet authored Jul 20, 2015
  71a71485
- [NVPTX] make load on global readonly memory to use ldg · 48a9bdc6
  Jingyue Wu authored Jul 20, 2015
  48a9bdc6
- [Hexagon] Generate MUX from conditional transfers when dot-new not possible · 92172204
  Krzysztof Parzyszek authored Jul 20, 2015
  92172204
- MIR Serialization: Initial serialization of machine constant pools. · ab980499
  Alex Lorenz authored Jul 20, 2015
  ab980499
- [ImplicitNullChecks] Work with implicit defs. · 93d608c3
  Sanjoy Das authored Jul 20, 2015
  93d608c3
- MIR Parser: Add support for quoted named global value operands. · b29554da
  Alex Lorenz authored Jul 20, 2015
  b29554da
- [AArch64] Change EON pattern to match more often. · 3da0ea7f
  Chad Rosier authored Jul 20, 2015
  3da0ea7f
- Add missing test for r242296 (vec_sld) · 19dbd6c6
  Bill Schmidt authored Jul 20, 2015
  19dbd6c6
- AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops · 70580f83
  Tom Stellard authored Jul 20, 2015
  70580f83
Jul 19, 2015
- [X86][SSE] Tidied up vector CTLZ/CTTZ. NFCI. · 23a29daf
  Simon Pilgrim authored Jul 19, 2015
  23a29daf
- AVX-512: Floating point conversions for SKX - DAG Lowering. · 17b90605
  Elena Demikhovsky authored Jul 19, 2015
  17b90605
Jul 18, 2015
- [X86][SSE] Added additional fp/int tests. · 8c81678d
  Simon Pilgrim authored Jul 18, 2015
  8c81678d
- Refreshed tests. · c77f72c4
  Simon Pilgrim authored Jul 18, 2015
  c77f72c4
- Refreshed tests and reordered in descending integer size. · 036db526
  Simon Pilgrim authored Jul 18, 2015
  036db526
- Tidyup shufflevector calls - don't repeat inputs if you can avoid it. · 27e130f1
  Simon Pilgrim authored Jul 18, 2015
  27e130f1
- ARM: Enable MachineScheduler and disable PostRAScheduler for swift. · 9e859806
  Matthias Braun authored Jul 17, 2015
  9e859806
- ARM: Add scheduling information for LDRLIT instructions to swift scheduling model · 141d1c9d
  Matthias Braun authored Jul 17, 2015
  141d1c9d
- [RAGreedy] Add an experimental deferred spilling feature. · 11922946
  Quentin Colombet authored Jul 17, 2015
  11922946
- MIR Parser: Allow the dollar characters in all of the identifier tokens. · 484903ec
  Alex Lorenz authored Jul 17, 2015
  484903ec
Jul 17, 2015
- Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift." · 5a6d5bc1
  Adam Nemet authored Jul 17, 2015
  5a6d5bc1
- Use inbounds GEPs for memcpy and memset lowering · b09cfb51
  Eli Bendersky authored Jul 17, 2015
  b09cfb51
- Make global aliases have symbol size equal to their type · 9ca9ca28
  John Brawn authored Jul 17, 2015
  9ca9ca28
- ARM: Enable MachineScheduler and disable PostRAScheduler for swift. · 2d8315f8
  Matthias Braun authored Jul 17, 2015
  2d8315f8
- Only do fmul (fadd x, x), c combine if the fadd only has one use · cabe02e1
  Matt Arsenault authored Jul 17, 2015
  cabe02e1
- Use small encodings for constants when possible. · 494a381e
  Rafael Espindola authored Jul 17, 2015
  494a381e