Vector selects are cheap on NEON. They get lowered to a vbsl instruction.

radar://13158753

llvm-svn: 174631

22 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174615

Use sub0-15 everywhere.

Patch by: Michel Dänzerr

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 174610

These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609

llvm-svn: 174607

For example, when we are doing mips16 hard float or soft float.

llvm-svn: 174583

llvm-svn: 174580

llvm-svn: 174546

account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).

llvm-svn: 174542

Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI.  Rename
things to clarify this.  Also delete some code that's been commented out
for a long time.

llvm-svn: 174526

Only implemented for R600 so far.  SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
  - Add support for i8 zext load from stack.
  - Coding style fixes

v3:
  - Don't reserve registers for indirect addressing when it isn't
    being used.
  - Fix bug caused by LLVM limiting the number of SubRegIndex
    declarations.

v4:
  - Fix 64-bit defines

llvm-svn: 174525

Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

llvm-svn: 174518

These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.

llvm-svn: 174496

This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

llvm-svn: 174495

Use the validateTargetOperandClass() hook to match literal '#0' operands in
InstAlias definitions. Previously this required per-instruction C++ munging of the
operand list, but not is handled as a natural part of the matcher. Much better.

No additional tests are required, as the pre-existing tests for these instructions
exercise the new behaviour as being functionally equivalent to the old.

llvm-svn: 174488

pointer in function prologs/epilogs. The opcodes should depend on the
data model (LP64 vs. ILP32) rather than the architecture bit-ness.

llvm-svn: 174446

is a vararg function.

The original code was examining flag OutputArg::IsFixed to determine whether
CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this
flag is often set to false when the function being analyzed is a non-variadic
function.

llvm-svn: 174442

         zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429

llvm-svn: 174415

llvm-svn: 174414

llvm-svn: 174413

llvm-svn: 174412

llvm-svn: 174411

llvm-svn: 174410

llvm-svn: 174409

llvm-svn: 174408

llvm-svn: 174407

llvm-svn: 174406

llvm-svn: 174402

Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

llvm-svn: 174400

The liveout lists are about to be removed from MRI, this is the only
place they were used after register allocation.

Get the live out V registers directly from the return instructions
instead.

llvm-svn: 174399

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174395

Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.

Patch By: Vadim Girlin

v2[Vincent Lejeune]: Rebased against current llvm master

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174394

Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392

Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174391

llvm-svn: 174390

for the existing instructions.

llvm-svn: 174389

llvm-svn: 174387

This should fix the valgrind buildbot failure.

llvm-svn: 174375

Also adds some costs for vector integer float conversions.

llvm-svn: 174371