vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984

llvm-svn: 90925

Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.

llvm-svn: 90922

- Also support the 'q' NEON registers asm code.

llvm-svn: 90894

Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!

llvm-svn: 90819

current form, it is too expensive in compile time.

llvm-svn: 90781

llvm-svn: 90742

llvm-svn: 90740

llvm-svn: 90739

llvm-svn: 90737

in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724

llvm-svn: 90656

- Privatize a typedef.
- Call the InvalidateEntry when refining a type.

llvm-svn: 90655

llvm-svn: 90640

llvm-svn: 90639

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

Remove an unneeded include.

llvm-svn: 90625

Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.

llvm-svn: 90608

llvm-svn: 90588

llvm-svn: 90490

llvm-svn: 90429

llvm-svn: 90428

llvm-svn: 90419

both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417

llvm-svn: 90383

function, converting "dyn_cast" to "cast", asserting the correct things, and
other general cleanups.

llvm-svn: 90371

llvm-svn: 90370

llvm-svn: 90366

Patch by Howard Hinnant!

llvm-svn: 90365

that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.

llvm-svn: 90362

No functionality change.

llvm-svn: 90336

llvm-svn: 90246

llvm-svn: 90243

For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173

llvm-svn: 90166

llvm-svn: 90165

for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144

llvm-svn: 90141

divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.

llvm-svn: 90108

llvm-svn: 90050