optimize addressing modes.  This allows us to optimize things like isel-sink2.ll
into:

	movl	4(%esp), %eax
	cmpb	$0, 4(%eax)
	jne	LBB1_2	## F
LBB1_1:	## TB
	movl	$4, %eax
	ret
LBB1_2:	## F
	movzbl	7(%eax), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpb	$0, 4(%eax)
	leal	4(%eax), %eax
	jne	LBB1_2	## F
LBB1_1:	## TB
	movl	$4, %eax
	ret
LBB1_2:	## F
	movzbl	3(%eax), %eax
	ret

This shrinks (e.g.) 403.gcc from 1133510 to 1128345 lines of .s.

Note that the 2008-10-16-SpillerBug.ll testcase is dubious at best, I doubt
it is really testing what it thinks it is.

llvm-svn: 60068

llvm-svn: 60067

llvm-svn: 60066

change AnnotationManager to use 'const char*' instead of std::string. this fixes the leakage of those strings and avoids the creation of such strings in static cosntructors (should result in a little improvement of startup time)

llvm-svn: 60064

llvm-svn: 60052

llvm-svn: 60049

llvm-svn: 60048

llvm-svn: 60047

llvm-svn: 60046

llvm-svn: 60045

llvm-svn: 60044

llvm-svn: 60043

convertToSignExtendedInteger should return opInvalidOp instead of asserting if sematics of float does not allow arithmetics.

llvm-svn: 60042

llvm-svn: 60041

llvm-svn: 60039

(a) Remove conditionally removed code in SelectXAddr. Basically, hope for the
    best that the A-form and D-form address predicates catch everything before
    the code decides to emit a X-form address.
(b) Expand vector store test cases to include the usual suspects.

llvm-svn: 60034

llvm-svn: 60030

llvm-svn: 60016

llvm-svn: 60015

if the operands have the same sign and the sum has sign opposite to that of the
operands."

llvm-svn: 60014

can recursively match things) and scales by 0 by ignoring them.
This triggers once in 403.gcc, saving 1 (!!!!) instruction in the 
whole huge app.

llvm-svn: 60013

into a new AddressingModeMatcher class.  This makes it easier
to reason about and reduces passing around of stuff, but has
no functionality change.

llvm-svn: 60012

new FindMaximalLegalAddressingModeForOperation helper method.

llvm-svn: 60011

llvm-svn: 60010

llvm-svn: 60009

llvm-svn: 60008

they were too tight according to bug 3126.

Fix bug 3126.

llvm-svn: 60006

llvm-svn: 60001

llvm-svn: 60000

introduce any new spilling; it just uses unused registers.

Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.

llvm-svn: 59999

llvm-svn: 59998

llvm-svn: 59992

llvm-svn: 59990

llvm-svn: 59989

llvm-svn: 59986

llvm-svn: 59985

llvm-svn: 59981

simplify header dependencies for front-ends that just want to choose
a scheduler and don't need all the scheduling machinery declarations.

llvm-svn: 59978

llvm-svn: 59977

llvm-svn: 59976