llvm-svn: 37607

llvm-svn: 37606

llvm-svn: 37602

for tied register constraints.

llvm-svn: 37601

llvm-svn: 37599

llvm-svn: 37597

integer constant SCEV.

llvm-svn: 37596

llvm-svn: 37595

llvm-svn: 37593

This created an ambiguity for expandInTy to decide when to use
sign-extension or zero-extension, but it turns out that most of its callers
don't actually need a type conversion, now that LLVM types don't have
explicit signedness. Drop expandInTy in favor of plain expand, and change
the few places that actually need a type conversion to do it themselves.

llvm-svn: 37591

llvm-svn: 37590

integer ops.  This implements Transforms/InstCombine/and-or-not.ll
test3/test4, and finishes off PR1510

llvm-svn: 37589

AND vectors.

llvm-svn: 37586

llvm-svn: 37585

1. ~(~X | Y) === (X & ~Y)
2. (A|B) & ~(A&B) -> A^B

This allows us to transform  ~(~(a|b) | (a&b)) -> a^b.

This implements PR1510 for scalar values.

llvm-svn: 37584

operations from Duraids example.

llvm-svn: 37582

llvm-svn: 37581

If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.

llvm-svn: 37580

llvm-svn: 37579

llvm-svn: 37578

llvm-svn: 37577

implementation for x86.

llvm-svn: 37576

llvm-svn: 37575

llvm-svn: 37574

llvm-svn: 37572

llvm-svn: 37571

turned on.  Likewise for scanning of invokes to mark landing pads.

llvm-svn: 37570

VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.

This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.

llvm-svn: 37569

correct types for the result vector, even though it is currently bitcasted
to a different type immediately.

llvm-svn: 37568

crashing but breaks exception handling.  The problem
described in PR1224 is that invoke is a terminator that
can produce a value.  The value may be needed in other
blocks.  The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available.  The fix that was applied was to do invoke
lowering earlier, before writing values to registers.

The problem this causes is that the code to copy values
to registers can be output after the invoke call.  If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute.  If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.

So revert the original fix and simply skip invoke values
in the general copying to registers code.  Instead copy
the invoke value to a register in the invoke lowering code.

llvm-svn: 37567

llvm-svn: 37566

llvm-svn: 37565

llvm-svn: 37564

llvm-svn: 37562

llvm-svn: 37561

common dominator.

llvm-svn: 37559

Refactor some code, and fix test/Transforms/GVNPRE/2007-06-12-NoExit.ll by being more careful when using
post-dominator information.

llvm-svn: 37556

llvm-svn: 37554

Remove unused PostETForest.

llvm-svn: 37551

Fix a few more bugs, including an instance of walking in reverse topological rather than topological order.  This
fixes a testcase extracted from llvm-test.

llvm-svn: 37550