handles dead implicit results more aggressively.  More
to come, I think this is now just a data entry problem.

llvm-svn: 99486

        addl    $12, %esp
        popl    %esi
        popl    %edi
        popl    %ebx
        popl    %ebp
        jmpl    *__Block_deallocator-L1$pb(%esi)  # TAILCALL

The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.

The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.

llvm-svn: 99455

--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450

llvm-svn: 99440

not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.

llvm-svn: 99435

llvm-svn: 99434

llvm-svn: 99423

and defining the add pattern with Pat<>, eliminating a use of
parallel.

llvm-svn: 99375

llvm-svn: 99370

ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.

llvm-svn: 99369

llvm-svn: 99360

llvm-svn: 99359

llvm-svn: 99358

This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345

Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

llvm-svn: 99320

MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.

llvm-svn: 99249

MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.

llvm-svn: 99248

llvm-svn: 99245

MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC.

llvm-svn: 99102

llvm-svn: 99097

caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.

llvm-svn: 99032

that they are dead.

llvm-svn: 99000

override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980

MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98972

 - MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

llvm-svn: 98955

llvm-svn: 98954

llvm-svn: 98950

MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.

llvm-svn: 98947

dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934

can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930

llvm-svn: 98919

to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903

llvm-svn: 98881

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880

llvm-svn: 98864

llvm-svn: 98862

temporary workaround for matching inc/dec on x86_64 to the correct instruction.
 - This hack will eventually be replaced with a robust mechanism for handling
   matching instructions based on the available target features.

llvm-svn: 98858

llvm-svn: 98855

files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839