llvm-svn: 139078

well.

Also, clean up the flow of the code a bit, and factor things more
nicely.

Finally, add the test case that was missing from my previous
commit (sorry), with new tests added to cover temporaries and other fun
cases.

llvm-svn: 139077

values that the resume instruction uses.
PR10850

llvm-svn: 139076

reference members of classes. We've had several bugs reported because of
this, and there's no reason not to flag it right away in the compiler.

Comments especially welcome on the strategy for implementing this
warning (IE, what should trigger this?) and on the text of the warning
itself.

I'm going to extend this to cover obvious cases with temporaries and
beef up the test cases some in subsequent patches. I'll then run it over
a large codebase and make sure its not misbehaving before I add it to
-Wall or turn it on by default. I think this one might be a good
candidate for on by default.

llvm-svn: 139075

llvm-svn: 139074

the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073

llvm-svn: 139072

llvm-svn: 139071

llvm-svn: 139070

llvm-svn: 139069

duplicate it for AVX mode.

llvm-svn: 139068

llvm-svn: 139067

that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066

pattern should be matched

llvm-svn: 139065

llvm-svn: 139064

it!

llvm-svn: 139063

llvm-svn: 139062

llvm-svn: 139061

OptForSize pattern

llvm-svn: 139060

If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059

llvm-svn: 139058

The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057

It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056

llvm-svn: 139055

llvm-svn: 139054

llvm-svn: 139053

llvm-svn: 139052

llvm-svn: 139051

llvm-svn: 139050

Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049

llvm-svn: 139048

llvm-svn: 139047

llvm-svn: 139046

llvm-svn: 139044

llvm-svn: 139043

llvm-svn: 139042

// rdar://10033896

llvm-svn: 139041

For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040

llvm-svn: 139039

llvm-svn: 139038