No functional change, just moved header files.

Targets can inject custom passes between register allocation and
rewriting. This makes it possible to tweak the register allocation
before rewriting, using the full global interference checking available
from LiveRegMatrix.

llvm-svn: 168806

This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.

llvm-svn: 168773

llvm-svn: 168772

This fixes a hole in the "cheap" alias analysis logic implemented within
the DAG builder itself, regardless of whether proper alias analysis is
enabled. It now handles this pattern produced by LSR+CodeGenPrepare.

%sunkaddr1 = ptrtoint * %obj to i64
%sunkaddr2 = add i64 %sunkaddr1, %lsr.iv
%sunkaddr3 = inttoptr i64 %sunkaddr2 to i32*
store i32 %v, i32* %sunkaddr3

llvm-svn: 168768

llvm-svn: 168767

The *Impl class no longer serves a purpose now that the super-class
implementation is in CodeGen.

llvm-svn: 168759

The Target library is not allowed to depend on the large CodeGen
library, but the TRI and TII classes provide abstract interfaces that
require both caller and callee to link to CodeGen.

The implementation files for these classes provide default
implementations of some of the hooks. These methods may need to
reference CodeGen, so they belong in that library.

We already have a number of methods implemented in the
TargetInstrInfoImpl sub-class because of that. I will merge that class
into the parent next.

llvm-svn: 168758

llvm-svn: 168751

the coding standard would like.

llvm-svn: 168737

llvm-svn: 168736

boundaries.

Given the following case:
BB0
  %vreg1<def> = SUBrr %vreg0, %vreg7
  %vreg2<def> = COPY %vreg7
BB1
  %vreg10<def> = SUBrr %vreg0, %vreg2
We should be able to CSE between SUBrr in BB0 and SUBrr in BB1.

rdar://12462006

llvm-svn: 168717

llvm-svn: 168712

argument.  Instead, use a pair of .local and .comm directives.

This avoids spurious differences between binaries built by the
integrated assembler vs. those built by the external assembler,
since the external assembler may impose alignment requirements
on .lcomm symbols where the integrated assembler does not.

llvm-svn: 168704

and O0 + debug codegen.

llvm-svn: 168680

llvm-svn: 168670

llvm-svn: 168664

llvm-svn: 168663

llvm-svn: 168660

llvm-svn: 168659

llvm-svn: 168644

add a TODO for starting.

llvm-svn: 168643

llvm-svn: 168638

llvm-svn: 168637

llvm-svn: 168633

r168627), we no longer need to call the freezeReservedRegs() function a second
time.  Previously, this pass was conservatively adding the FP to the set of
reserved registers, requiring the second update to the reserved registers.
rdar://12719844

llvm-svn: 168631

r168627), we no longer need to call the freezeReservedRegs() function a second
time.  Previously, this pass was conservatively adding the FP to the set of
reserved registers, requiring the second update to the reserved registers.
rdar://12719844

llvm-svn: 168630

llvm-svn: 168622

llvm-svn: 168608

llvm-svn: 168557

Remove duplicate check of LimitFloatPrecision. It was already checked earlier before IsExp10 could be set to true.

llvm-svn: 168553

llvm-svn: 168551

Remove redundant calls to getCurDebugLoc in visitIntrinsicCall. It's already called at the start of the function and captured in a local variable.

llvm-svn: 168548

llvm-svn: 168546

llvm-svn: 168538

llvm-svn: 168524

llvm-svn: 168507

llvm-svn: 168498

isOperationLegal. Thanks to Craig Topper for pointing this out.

llvm-svn: 168485

llvm-svn: 168481

llvm-svn: 168402