bugpoint-ing, it may turn into something else.

llvm-svn: 156998

llvm-svn: 156996

separate side table, using the handy SequenceToOffsetTable class.  This encodes all
these weird things into another 256 bytes, allowing all intrinsics to be encoded this way.

llvm-svn: 156995

Patch by Meador Inge.

llvm-svn: 156989

llvm-svn: 156986

SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons.

llvm-svn: 156985

for future expansion, no functionality change yet though.

llvm-svn: 156979

are only rejected because they can't be encoded into a 32-bit unit, not because
they contain an unencodable feature.

llvm-svn: 156978

intrinsics that use passed-in arguments.

llvm-svn: 156977

compatibility with LLVM 2.x bitcode files.

llvm-svn: 156976

llvm-svn: 156975

llvm-svn: 156973

TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.

This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.

llvm-svn: 156960

llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958

llvm-svn: 156955

When widening an existing <def,reads-undef> operand to a super-register,
it may be necessary to clear the <undef> flag because the wider register
is now read-modify-write through the instruction.

Conversely, it may be necessary to add an <undef> flag when the
coalescer turns a full-register def into a sub-register def, but the
larger register wasn't live before the instruction.

This happens in test/CodeGen/ARM/coalesce-subregs.ll, but the test
is too small for the <undef> flags to affect the generated code.

llvm-svn: 156951

on MIPS where they are not implemented.

llvm-svn: 156935

Added LLIMCJITMemoryManager to the lli. This manager will be used for MCJIT instead of DefaultJIMMemoryManager.
It's more flexible for MCJIT tasks, in addition it's provides a invalidation instruction cache for code sections which will be used before JIT code will be executed.

llvm-svn: 156933

llvm-svn: 156917

named metadata list, unlike all the other global objects (global variables,
functions, aliases), so add that for consistency.

llvm-svn: 156915

options, to enable easier testing of the innards of LLVM that are
enabled by such optimization strategies.

Note that this doesn't provide the (much needed) function attribute
support for -Oz (as opposed to -Os), but still seems like a positive
step to better test the logic that Clang currently relies on.

Patch by Patrik Hägglund.

llvm-svn: 156913

llvm-svn: 156909

generated code (for Intrinsic::getType) into a table.  This handles common cases right now,
but I plan to extend it to handle all cases and merge in type verification logic as well
in follow-on patches.

llvm-svn: 156905

llvm-svn: 156902

llvm-svn: 156896

llvm-svn: 156881

It is now possible to coalesce weird skewed sub-register copies by
picking a super-register class larger than both original registers. The
included test case produces code like this:

  vld2.32 {d16, d17, d18, d19}, [r0]!
  vst2.32 {d18, d19, d20, d21}, [r0]

We still perform interference checking as if it were a normal full copy
join, so this is still quite conservative. In particular, the f1 and f2
functions in the included test case still have remaining copies because
of false interference.

llvm-svn: 156878

It is possible to coalesce two overlapping registers to a common
super-register that it larger than both of the original registers.

The important difference is that it may be necessary to rewrite DstReg
operands as well as SrcReg operands because the sub-register index has
changed.

This behavior is still disabled by CoalescerPair.

llvm-svn: 156869

This can happen when widening a virtual register to a super-register
class.

llvm-svn: 156867

There is no need to look at an always null SrcIdx.

llvm-svn: 156866

 - Hopefully fixes PR11600 (untested).

llvm-svn: 156865

llvm-svn: 156864

llvm-svn: 156857

llvm-svn: 156852

-macho to disassemble the last symbol to the end of the section.

llvm-svn: 156850

this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r)

llvm-svn: 156849

Now both SrcReg and DstReg can be sub-registers of the final coalesced
register.

CoalescerPair::setRegisters still rejects such copies because
RegisterCoalescer doesn't yet handle them.

llvm-svn: 156848

llvm-svn: 156847

This feature avoids creating edges in the scheduler's dependence graph
for non-aliasing memory operations according to whichever alias
analysis is available. It has been fully tested in Hexagon. Before
making this default, it needs to be extended to handle multiple
MachineMemOperands, compile time needs more evaluation, and
benchmarking on X86 and ARM is needed.

Patch by Sergei Larin!

llvm-svn: 156842

that has more than one symbol.  The last symbol was not being disassembled to
the end of the section.

llvm-svn: 156840