- Sep 30, 2013
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Matt Arsenault authored
Currently it will insert an illegal bitcast. Arguably, the address space argument should be added for the creation case. llvm-svn: 191702
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Matt Arsenault authored
The test's output doesn't change, but this ensures this is actually hit with a different address space. llvm-svn: 191701
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Matt Arsenault authored
llvm-svn: 191699
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Manman Ren authored
No functionality change. llvm-svn: 191696
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Anders Waldenborg authored
This makes it consistent with other function pointers used in llvm-c Differential Revision: http://llvm-reviews.chandlerc.com/D1712 llvm-svn: 191693
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Tilmann Scheller authored
Changing the diagnostic message for out of range branch targets in 191686 broke the tests. The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics. llvm-svn: 191691
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Manman Ren authored
llvm-svn: 191690
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Manman Ren authored
llvm-svn: 191689
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Jack Carter authored
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
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Jack Carter authored
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
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Tilmann Scheller authored
Fix some LLVM Coding Standards violations. No changes in functionality. llvm-svn: 191686
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Jack Carter authored
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
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Jack Carter authored
and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
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Tilmann Scheller authored
llvm-svn: 191683
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Rafael Espindola authored
Patch by Richard Sandiford. llvm-svn: 191680
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Rafael Espindola authored
This reverts commit r191670. It was causing build failures on the msvc bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio llvm-svn: 191679
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Tilmann Scheller authored
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
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Arnold Schwaighofer authored
Those writes really need two/three uops. llvm-svn: 191677
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Benjamin Kramer authored
llvm-svn: 191676
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Benjamin Kramer authored
llvm-svn: 191675
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Benjamin Kramer authored
Defines away the issue where cast<Instruction> would fail because constant folding happened. Also slightly cleaner. llvm-svn: 191674
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Benjamin Kramer authored
Inspired by the object from the SLPVectorizer. This found a minor bug in the debug loc restoration in the vectorizer where the location of a following instruction was attached instead of the location from the original instruction. llvm-svn: 191673
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Benjamin Kramer authored
They don't depend on the templated stuff. llvm-svn: 191672
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Arnold Schwaighofer authored
For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
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Rafael Espindola authored
Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with MSVC and Mingw as well as re-enabling the associated test. Patch by Greg Bedwell! llvm-svn: 191670
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Joey Gouly authored
when it was actually a Constant*. There are quite a few other casts to Instruction that might have the same problem, but this is the only one I have a test case for. llvm-svn: 191668
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Tilmann Scheller authored
llvm-svn: 191664
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Richard Sandiford authored
For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. llvm-svn: 191663
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Richard Sandiford authored
llvm-svn: 191661
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Richard Sandiford authored
The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. llvm-svn: 191660
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Richard Sandiford authored
Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. llvm-svn: 191659
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Daniel Sanders authored
It now points to the equivalent page on imgtec.com llvm-svn: 191658
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Richard Sandiford authored
llvm-svn: 191656
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Richard Sandiford authored
I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. llvm-svn: 191655
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Craig Topper authored
Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. llvm-svn: 191652
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Craig Topper authored
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits. llvm-svn: 191650
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Craig Topper authored
Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
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- Sep 29, 2013
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Benjamin Kramer authored
Those can occur in dead code. PR17402. llvm-svn: 191644
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Benjamin Kramer authored
llvm-svn: 191643
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Benjamin Kramer authored
llvm-svn: 191638
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