llvm-svn: 115988

llvm-svn: 115951

llvm-svn: 115950

llvm-svn: 115949

do one find().

llvm-svn: 115929

llvm-svn: 115928

This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875

llvm-svn: 115874

llvm-svn: 115835

llvm-svn: 115833

llvm-svn: 115802

llvm-svn: 115792

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

llvm-svn: 115710

reusable, but that is no longer relevant since a split will always replace the
original.

llvm-svn: 115709

llvm-svn: 115708

llvm-svn: 115696

never kept after splitting.

Keeping the original interval made sense when the split region doesn't modify
the register, and the original is spilled. We can get the same effect by
detecting reloaded values when spilling around copies.

llvm-svn: 115695

llvm-svn: 115694

erasing it from the visited set. That ensures we create the right phi defs.

llvm-svn: 115666

Insert copy after defining instruction.

Fix LiveIntervalMap::extendTo to properly handle live segments starting before
the current basic block.

Make sure the open live range is extended to the inserted copy's use slot.

llvm-svn: 115665

llvm-svn: 115650

llvm-svn: 115649

Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
having to do a double cast (uint64_t --> double --> float).  This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.

llvm-svn: 115634

    //   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = srl i32 %b, 1                                                                                                                                                                        
    //   brcond i32 %c ...                                                                                                                                                                         
    //                                                                                                                                                                                             
    // into                                                                                                                                                                                        
    //                                                                                                                                                                                             
    //   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = setcc eq %b, 0                                                                                                                                                                       
    //   brcond %c ...

Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.

This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.

llvm-svn: 115571

Removed the older style (in-allocator) problem construction system from the PBQP allocator. Problem construction is now done exclusively with the new builders.

llvm-svn: 115502

llvm-svn: 115408

scheduling change in svn 115121.  The CriticalAntiDepBreaker had bad
liveness information.  It was calculating the KillIndices for one scheduling
region in a basic block, rescheduling that region so the KillIndices were
no longer valid, and then using those wrong KillIndices to make decisions
for the next scheduling region.  I've not been able to reduce a small
testcase for this.  Radar 8502534.

llvm-svn: 115400

RemoveCopyByCommutingDef.

llvm-svn: 115386

LiveInterval::MergeValueNumberInto instead of trying to extend LiveRanges and
getting it wrong.

This fixed PR8249 where a valno with a multi-segment live range was defined by
an identity copy created by RemoveCopyByCommutingDef. Some of the live
segments disappeared.

llvm-svn: 115385

llvm-svn: 115384

llvm-svn: 115378

llvm-svn: 115377

Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs.  For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.

llvm-svn: 115364

Fix code gen crash reported in PR 8235. We still lose debug info for the unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case.

llvm-svn: 115323

llvm-svn: 115310

llvm-svn: 115300

llvm-svn: 115294

The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

edited during emission.

If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.

This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.

The fix is to uipdate stale MBB pointers whenever a block is split during
emission.

llvm-svn: 115191