llvm-svn: 47597

llvm-svn: 47596

llvm-svn: 47595

GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.

llvm-svn: 47594

calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.

llvm-svn: 47593

vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.

llvm-svn: 47592

after legalize.  Just because a constant is legal (e.g. 0.0 in SSE) 
doesn't mean that its negated value is legal (-0.0).  We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.

llvm-svn: 47591

operands into inline asm block.

llvm-svn: 47589

llvm-svn: 47587

llvm-svn: 47585

llvm-svn: 47584

Take 2.

llvm-svn: 47583

llvm-svn: 47577

llvm-svn: 47576

pointed out that this isn't correct at -O0.

llvm-svn: 47575

llvm-svn: 47574

llvm-svn: 47573

and StoreSDNode into LSBaseSDNode.

llvm-svn: 47570

{S,U}MUL_LOHI with an unused high value.

llvm-svn: 47569

result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.

llvm-svn: 47567

llvm-svn: 47566

llvm-svn: 47563

a SignBitIsZero function to simplify a common use case.

llvm-svn: 47561

llvm-svn: 47558

All remat'ed loads cannot be folded into two-address code. Not just argument loads. This change doesn't really have any impact on codegen.

llvm-svn: 47557

llvm-svn: 47556

llvm-svn: 47555

of TokenFactor underneath chain (seems to be enough)

llvm-svn: 47554

that combines getValueType and MVT::getSizeInBits, since this
occurrs frequently.

llvm-svn: 47552

result and operand types are legal.

llvm-svn: 47546

llvm-svn: 47545

not safe.  This is fixed by more aggressively checking that the return slot is
not used elsewhere in the function.

llvm-svn: 47544

llvm-svn: 47542

Fix an issue where GVN would try to use an instruction before its definition when performing return slot optimization.

llvm-svn: 47541

out of illegal elements (BUILD_VECTOR).  Uses and beefs
up BUILD_PAIR, though it didn't really have to.  Like
most of LegalizeTypes, does not support soft-float.
This cures all "make check" vector building failures.

llvm-svn: 47537

%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534

llvm-svn: 47533

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47531

llvm-svn: 47529