- Oct 17, 2011
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Akira Hatanaka authored
llvm-svn: 142220
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- Oct 11, 2011
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Akira Hatanaka authored
that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
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- Oct 08, 2011
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Akira Hatanaka authored
llvm-svn: 141476
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Akira Hatanaka authored
llvm-svn: 141475
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Akira Hatanaka authored
llvm-svn: 141474
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Akira Hatanaka authored
conversion instructions. llvm-svn: 141473
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- Sep 29, 2011
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Jakob Stoklund Olesen authored
It broke the unit tests. Please reapply with tests fixed. llvm-svn: 140735
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- Sep 28, 2011
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Akira Hatanaka authored
multiclasses. llvm-svn: 140731
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Akira Hatanaka authored
llvm-svn: 140705
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Akira Hatanaka authored
llvm-svn: 140704
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Akira Hatanaka authored
llvm-svn: 140661
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Akira Hatanaka authored
of the instruction definitions using Pat<>. llvm-svn: 140644
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- Sep 23, 2011
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Akira Hatanaka authored
complain it cannot infer types in patterns. Fix a mistake in definition of SDT_MipsExtractElementF64. llvm-svn: 140354
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- Sep 09, 2011
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Akira Hatanaka authored
llvm-svn: 139405
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- Aug 16, 2011
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Akira Hatanaka authored
Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
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- Jun 07, 2011
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Akira Hatanaka authored
llvm-svn: 132718
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- May 24, 2011
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Akira Hatanaka authored
llvm-svn: 131927
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- May 12, 2011
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Akira Hatanaka authored
llvm-svn: 131233
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- May 09, 2011
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Eric Christopher authored
Patch by Liu <proljc@gmail.com>! llvm-svn: 131086
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- Apr 15, 2011
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Akira Hatanaka authored
llvm-svn: 129612
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Akira Hatanaka authored
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. llvm-svn: 129606
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Akira Hatanaka authored
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
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Chris Lattner authored
Luis Felipe Strano Moraes! llvm-svn: 129558
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- Mar 31, 2011
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Akira Hatanaka authored
llvm-svn: 128650
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- Mar 04, 2011
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Bruno Cardoso Lopes authored
llvm-svn: 127003
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- Dec 23, 2010
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Chris Lattner authored
llvm-svn: 122513
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- Aug 17, 2010
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Chris Lattner authored
llvm-svn: 111241
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- Mar 28, 2010
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Chris Lattner authored
llvm-svn: 99737
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- Jan 30, 2010
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Bruno Cardoso Lopes authored
llvm-svn: 94914
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- Nov 16, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 88887
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- Nov 12, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 86895
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- Nov 10, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 86651
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- Oct 29, 2009
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Dan Gohman authored
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
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- May 27, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 72483
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- Mar 21, 2009
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Bruno Cardoso Lopes authored
Handle odd registers allocation in FGR32. llvm-svn: 67422
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- Aug 04, 2008
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Bruno Cardoso Lopes authored
llvm-svn: 54315
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- Jul 30, 2008
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Bruno Cardoso Lopes authored
access). Added pattern to match bitconvert node. Fixed MTC1 asm string bug. llvm-svn: 54229
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- Jul 29, 2008
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Bruno Cardoso Lopes authored
llvm-svn: 54167
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- Jul 28, 2008
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Bruno Cardoso Lopes authored
Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. llvm-svn: 54139
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- Jul 09, 2008
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Bruno Cardoso Lopes authored
llvm-svn: 53272
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