llvm-svn: 152443

Make Binary::TypeID more granular, to distinguish between ELF 32/64 little/big

llvm-svn: 152435

to count the number of phis changed, not the number visited.

llvm-svn: 152425

traversal, consider nodes for which the only successors are backedges
which the traversal is ignoring to be exit nodes. This fixes a problem
where the bottom-up traversal was failing to visit split blocks along
split loop backedges. This fixes rdar://10989035.

llvm-svn: 152421

prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414

negative switch cases if the branch condition is known to be positive.
Inspired by a recent improvement to GCC's VRP.

llvm-svn: 152405

Patch by Tom Stellard!

llvm-svn: 152400

it to analyze extractvalue(llvm.[us](add|sub).with.overflow.*) intrinsics!

llvm-svn: 152398

llvm-svn: 152393

llvm-svn: 152391

llvm-svn: 152390

llvm-svn: 152382

llvm-svn: 152374

llvm-svn: 152373

introduced. Specifically, there are cost reductions for all
constant-operand icmp instructions against an alloca, regardless of
whether the alloca will in fact be elligible for SROA. That means we
don't want to abort the icmp reduction computation when we abort the
SROA reduction computation. That in turn frees us from the need to keep
a separate worklist and defer the ICmp calculations.

Use this new-found freedom and some judicious function boundaries to
factor the innards of computing the cost factor of any given instruction
out of the loop over the instructions and into static helper functions.
This greatly simplifies the code, and hopefully makes it more clear what
is happening here.

Reviewed by Eric Christopher. There is some concern that we'd like to
ensure this doesn't get out of hand, and I plan to benchmark the effects
of this change over the next few days along with some further fixes to
the inline cost.

llvm-svn: 152368

Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078

llvm-svn: 152366

llvm-svn: 152360

llvm-svn: 152356

llvm-svn: 152346

buildbots.  Original commit message:

[ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline, reapplied
with a fix for the longstanding over-read of 32-bit pointer values.

llvm-svn: 152304

llvm-svn: 152301

with a fix for the longstanding over-read of 32-bit pointer values.

llvm-svn: 152300

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*".

ConstCaseIt is just a read-only iterator.
CaseIt is read-write iterator; it allows to change case successor and case value.

Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters.

Main way of iterator usage looks like this:
SwitchInst *SI = ... // intialize it somehow

for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) {
  BasicBlock *BB = i.getCaseSuccessor();
  ConstantInt *V = i.getCaseValue();
  // Do something.
}

If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method.
If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method.

There are also related changes in llvm-clients: klee and clang.

llvm-svn: 152297

inline.", which is breaking the bots in a way I don't understand.

llvm-svn: 152295

llvm-svn: 152290

llvm-svn: 152288

For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.

llvm-svn: 152285

analysis to be methods on the cost analysis's function info object
instead of the code metrics object. These really are just users of the
code metrics, they're building the information for the function's
analysis.

This is the first step of growing the amount of information we collect
about a function in order to cope with pair-wise simplifications due to
allocas.

llvm-svn: 152283

llvm-svn: 152282

For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero: 

addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0

add $vr2, $vr1, $zero

llvm-svn: 152280

Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...

llvm-svn: 152278

The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.

rdar://11006355

llvm-svn: 152268

code that will be relocated into another memory space.
Now when relocations are resolved, the address of
the relocation in the host memory (where the JIT is)
is passed separately from the address that the
relocation will be at in the target memory (where
the code will run).

llvm-svn: 152264

llvm-svn: 152262

implement their own MachineScheduler.

llvm-svn: 152261

llvm-svn: 152260

llvm-svn: 152259

ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.

llvm-svn: 152258

llvm-svn: 152257

ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

llvm-svn: 152256