patches are also needed.

llvm-svn: 37070

test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069

llvm-svn: 37068

llvm-svn: 37067

llvm-svn: 37066

llvm-svn: 37065

llvm-svn: 37064

llvm-svn: 37063

llvm-svn: 37062

llvm-svn: 37061

llvm-svn: 37060

llvm-svn: 37059

llvm-svn: 37058

llvm-svn: 37057

llvm-svn: 37056

linkage or hidden visibility.

llvm-svn: 37055

CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054

llvm-svn: 37053

llvm-svn: 37052

llvm-svn: 37051

v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050

llvm-svn: 37048

llvm-svn: 37047

When marking a register as being implicitly defined, make sure to clear its partial use info as well.

llvm-svn: 37046

and used in the same module.

llvm-svn: 37044

llvm-svn: 37042

llvm-svn: 37040

llvm-svn: 37039

llvm-svn: 37038

just aids in readability and debugability of the output. No functional change.

llvm-svn: 37037

documentation to describe the desired behavior.

llvm-svn: 37036

in the reverse case the only difference is that the bits are returned in
reverse order.

llvm-svn: 37035

llvm-svn: 37034

-print-cfg-only except they use the ViewCFG function, which displays the
CFG rendered with graphviz with gv.

llvm-svn: 37033

of just using void*. This allows it to be used with graph adapters like
Inverse.

llvm-svn: 37032

addRequiredTransitive as addRequiredID is to addRequired.

llvm-svn: 37031

llvm-svn: 37028

llvm-svn: 37027

llvm-svn: 37026

types:
1. Functions to compute div/rem at the same time.
2. Further assurance that an APInt with 0 bitwidth cannot be constructed.
3. Left and right rotate operations.
4. An exactLogBase2 function which requires an exact power of two or it
   returns -1.

llvm-svn: 37025