llvm-svn: 143994

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989

llvm-svn: 143988

llvm-svn: 142216

llvm-svn: 142214

llvm-svn: 142211

source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210

and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207

llvm-svn: 142205

llvm-svn: 141761

instructions with two register operands derive from it.

llvm-svn: 141742

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

the real instructions.

llvm-svn: 141718

llvm-svn: 141715

llvm-svn: 141708

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

Mips64.

llvm-svn: 141618

zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608

for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603

llvm-svn: 141029

llvm-svn: 141028

llvm-svn: 141024

llvm-svn: 141017

registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015

llvm-svn: 140870

llvm-svn: 140862

llvm-svn: 140841

immediate.

llvm-svn: 140839

llvm-svn: 140806

llvm-svn: 140703

llvm-svn: 140446

the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953

and at least the 4 byte one will be needed to implement the .cfi_* directives.

llvm-svn: 120240

llvm-svn: 98954

the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924

llvm-svn: 80193