reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710

llvm-svn: 114703

llvm-svn: 114597

needs to happen for darwin.

llvm-svn: 114577

ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.

llvm-svn: 114554

llvm-svn: 114536

x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.

llvm-svn: 114534

Teaching the code generator about CR8-15, how to rex them up, etc.

llvm-svn: 114533

llvm-svn: 114531

llvm-svn: 114529

llvm-svn: 114528

-This line, and those below, will be ignored--

M    test/MC/AsmParser/X86/x86_instructions.s
M    lib/Target/X86/AsmParser/X86AsmParser.cpp

llvm-svn: 114527

llvm-svn: 114526

llvm-svn: 114523

can access the stack due to how it is generated though.

llvm-svn: 114522

used with stack slots, but hey, lets be safe.

llvm-svn: 114521

llvm-svn: 114515

call through gs-relative memory now.

llvm-svn: 114510

llvm-svn: 114508

by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.

llvm-svn: 114491

the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

llvm-svn: 114473

passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471

llvm-svn: 114468

llvm-svn: 114463

(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460

llvm-svn: 114453

SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446

llvm-svn: 114410

"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406

of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).

llvm-svn: 114404

into non-segment-relative copies.

llvm-svn: 114402

instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

llvm-svn: 114401

llvm-svn: 114391

For now, just disable folding the load into the call.

llvm-svn: 114386

llvm-svn: 114297

This fixes rdar://8396318.

llvm-svn: 114201

What a weird instruction.

llvm-svn: 114190

llvm-svn: 114116

wraps up r8418316

llvm-svn: 113949

for call.  Add this.

llvm-svn: 113948