llvm-svn: 119050

llvm-svn: 118987

darwin and, judging from the buildbots, Linux.
Removing it for now, but this is not the right fix,
Wesley please look at it.

llvm-svn: 118977

llvm-svn: 118974

llvm-svn: 118124

llvm-svn: 118122

llvm-svn: 118120

weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084

have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563

and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432

llvm-svn: 115580

llvm-svn: 114240

precision)

llvm-svn: 114028

moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.

llvm-svn: 114021

"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.

llvm-svn: 113903

printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251

This fixes another part of PR7792.

llvm-svn: 111057

instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894

Added two test cases to arm-tests.txt.

llvm-svn: 110880

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

Partial fix for PR7792.

llvm-svn: 110361

Partial fix for PR7792.

llvm-svn: 110358

llvm-svn: 110292

llvm-svn: 109946

disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974

as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929

transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915

Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817

VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784

llvm-svn: 101642

llvm-svn: 101559

case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557

this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529

to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527

Previous checkin tested Rn, #+/-Rm.

llvm-svn: 101418

am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415