llvm-svn: 111266

printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251

that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196

instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168

llvm-svn: 111154

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

Added two test cases to arm-tests.txt.

llvm-svn: 110880

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

llvm-svn: 110787

  memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785

llvm-svn: 110761

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110363

Partial fix for PR7792.

llvm-svn: 110361

Partial fix for PR7792.

llvm-svn: 110358

the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948

llvm-svn: 109813

Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.

llvm-svn: 109770

ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138

llvm-svn: 109696

and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

llvm-svn: 106362

llvm-svn: 106314

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

Not turning them on yet.

llvm-svn: 106295

llvm-svn: 106058

A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413

llvm-svn: 105350

llvm-svn: 104980

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

ISD::. No functional change.

llvm-svn: 104734

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

llvm-svn: 104114

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102