llvm-svn: 158250

inserted after the shift-left-logical node.

llvm-svn: 157937

This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929

llvm-svn: 157885

llvm-svn: 157872

llvm-svn: 157867

llvm-svn: 157866

llvm-svn: 157865

custom-lower unaligned load and store nodes.

llvm-svn: 157864

llvm-svn: 157863

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862

the MachineOperand type has a valid offset. 

llvm-svn: 157861

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837

CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730

Patch by Jack Carter.

llvm-svn: 157709

It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703

Benjamin Kramer.

llvm-svn: 157504

llvm-svn: 157496

Delete MipsExpandPseudo.

llvm-svn: 157495

llvm-svn: 157494

llvm-svn: 157493

llvm-svn: 157492

to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479

Expand test case for this.

Patch by Reed Kotler.

llvm-svn: 157410

First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408

llvm-svn: 157375

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

Patch by Jack Carter.

llvm-svn: 157093

Patch by Jack Carter.

llvm-svn: 157057

llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828

resolved.

llvm-svn: 156801

The purpose of this option is to silence error messages issued by machine
verifier passes and enable them to run to the end. If this option is not
provided, -verify-machineinstrs complains when it discovers there is a
non-terminator instruction (an instruction that is in a delay slot) after the
first terminator in a basic block.

llvm-svn: 156790

llvm-svn: 156696

the ones that get or set the frame index for the $gp save slot. 

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.

llvm-svn: 156695

is the $gp save slot.

llvm-svn: 156694

llvm-svn: 156693

- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692

- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.

llvm-svn: 156691

- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689