llvm-svn: 121853

llvm-svn: 121851

llvm-svn: 121850

llvm-svn: 121849

a wider mul if the wider mul is legal.

llvm-svn: 121848

llvm-svn: 121847

result, the top bits are truncated off anyway, just use SRL.

llvm-svn: 121846

llvm-svn: 121838

llvm-svn: 121837

llvm-svn: 121832

update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830

llvm-svn: 121829

llvm-svn: 121828

llvm-svn: 121827

llvm-svn: 121826

llvm-svn: 121825

llvm-svn: 121824

llvm-svn: 121823

llvm-svn: 121822

llvm-svn: 121820

immediate versions.

llvm-svn: 121819

this case involve a select that simplifies to itself.

llvm-svn: 121817

llvm-svn: 121816

llvm-svn: 121815

llvm-svn: 121812

llvm-svn: 121809

particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808

llvm-svn: 121807

llvm-svn: 121806

llvm-svn: 121805

llvm-svn: 121801

registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

llvm-svn: 121800

llvm-svn: 121798

llvm-svn: 121797

is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794

regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

llvm-svn: 121793

llvm-svn: 121792

warning in the opt build.

llvm-svn: 121791

llvm-svn: 121790

llvm-svn: 121789