llvm-svn: 77781

llvm-svn: 77768

llvm-svn: 77764

be more careful about the return value of runOnMachineFunction.

llvm-svn: 77758

llvm-svn: 77757

instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756

llvm-svn: 77755

 - Operands which are just a label should be parsed as immediates, not memory
   operands (from the assembler perspective).

 - Match a few more flavors of immediates.

 - Distinguish match functions for memory operands which don't take a segment
   register.

 - We match the .s for "hello world" now!

llvm-svn: 77745

llvm-svn: 77744

llvm-svn: 77743

thing is #if0'd out anyway.  Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.

llvm-svn: 77736

Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.

llvm-svn: 77728

indicate that it is a predicate, not an emitter.  This eliminates TAI
dependencies on Mangler and GlobalValue.

llvm-svn: 77726

because it just calls the default impl.

Remove the PPCDarwinTargetAsmInfo version of PreferredEHDataFormat because
it just returns DW_EH_PE_absptr unless on 10.6.  However, 10.6 doesn't support
PPC, so the default impl is just fine.

llvm-svn: 77724

llvm-svn: 77723

metadata related, which I'm waiting on to avoid conflicting with Devang.

llvm-svn: 77721

llvm-svn: 77718

MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708

to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705

  is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701

llvm-svn: 77692

shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.

llvm-svn: 77691

initialize method, which can be called when an MCContext is available.

llvm-svn: 77687

into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.

llvm-svn: 77679

llvm-svn: 77673

llvm-svn: 77667

failures when building assorted projects with clang.

--- Reverse-merging r77654 into '.':
U    include/llvm/CodeGen/Passes.h
U    include/llvm/CodeGen/MachineFunctionPass.h
U    include/llvm/CodeGen/MachineFunction.h
U    include/llvm/CodeGen/LazyLiveness.h
U    include/llvm/CodeGen/SelectionDAGISel.h
D    include/llvm/CodeGen/MachineFunctionAnalysis.h
U    include/llvm/Function.h
U    lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U    lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/MachineVerifier.cpp
U    lib/CodeGen/MachineFunction.cpp
U    lib/CodeGen/PrologEpilogInserter.cpp
U    lib/CodeGen/MachineLoopInfo.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D    lib/CodeGen/MachineFunctionAnalysis.cpp
D    lib/CodeGen/MachineFunctionPass.cpp
U    lib/CodeGen/LiveVariables.cpp

llvm-svn: 77661

 - This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.

llvm-svn: 77657

mechanism. To support this, make MachineFunctionPass a little more
complete.

llvm-svn: 77654

When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.

llvm-svn: 77642

llvm-svn: 77632

llvm-svn: 77627

llvm-svn: 77625

llvm-svn: 77622

llvm-svn: 77611

llvm-svn: 77602

classes. And define its SubRegClassList.

llvm-svn: 77601

llvm-svn: 77598

llvm-svn: 77584

Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582