llvm-svn: 108684

llvm-svn: 108683

assembling; remove crufty custom cleanup code.

llvm-svn: 108681

llvm-svn: 108680

llvm-svn: 108679

TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
 - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677

 - Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

llvm-svn: 108664

llvm-svn: 108626

llvm-svn: 108625

instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608

llvm-svn: 108603

llvm-svn: 108601

llvm-svn: 108588

stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.

llvm-svn: 108582

needsStackRealignment is currently checking the can conditions as well.

llvm-svn: 108581

and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

llvm-svn: 108567

llvm-svn: 108566

llvm-svn: 108565

Thumb2ITBlockPass.

llvm-svn: 108564

thus is a much more meaningful name.

llvm-svn: 108563

The isLive() method can read uninitialized memory, but it still gives correct
results.

llvm-svn: 108561

PowerPC.

llvm-svn: 108555

llvm-svn: 108547

llvm-svn: 108545

operands.

Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.

llvm-svn: 108540

pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536

llvm-svn: 108535

FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.

CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.

This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.

llvm-svn: 108529

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.

llvm-svn: 108454

llvm-svn: 108396

llvm-svn: 108387

instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386

lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.

llvm-svn: 108385

llvm-svn: 108368

llvm-svn: 108366

patch by Michael Spencer!

llvm-svn: 108342

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Patch by Brian Lucas. PR7636.

llvm-svn: 108332