x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829

llvm-svn: 45827

llvm-svn: 45823

llvm-svn: 45822

llvm-svn: 45819

Also, instructions with any nodes that are SDNPMayLoad also read memory.

llvm-svn: 45817

This is currently not set by anything.

llvm-svn: 45748

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.

llvm-svn: 45692

Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687

TargetInstrDescriptor class and shrink to 16-bits, saving a 
word in TargetInstrDescriptor.  Add some comments.

llvm-svn: 45686

just unconditionally use the def name of the instruction.

llvm-svn: 45684

over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677

llvm-svn: 45667

llvm-svn: 45656

instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654

intrinsic that writes to memory.

llvm-svn: 45650

occured in a pattern, but failed miserably.  The new code works for
any instruction that has a store in its pattern, including all the 
x86 mem op mem instructions.

The only target-independent code that uses this is branch folding,
so this won't change anything in practice.

llvm-svn: 45648

rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.

llvm-svn: 45647

llvm-svn: 45646

llvm-svn: 45645

llvm-svn: 45644

llvm-svn: 45643

llvm-svn: 45642

llvm-svn: 45641

llvm-svn: 45640

llvm-svn: 45639

out, DAGISelEmitter can compute it in its ctor, which simplifies some code.

Now we can use CodegenDAGPatterns in other parts of tblgen that want access
to dag pattern info, woo!

llvm-svn: 45636

The only difference in output is that we now print them in alphabetical 
order instead of reverse alphabetical order.

llvm-svn: 45635

llvm-svn: 45634

llvm-svn: 45633

Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.

llvm-svn: 45632

the VC++ 'nesting depth' issue.

llvm-svn: 45567

llvm-svn: 45563

if (!strcmp(Target, "x86")) {
  // ...
}
else
  IntrinsicID = Intrinsic::not_intrinsic;

llvm-svn: 45557

comparison for every builtin.  This reduces the depth of
the if/elseif chain dramatically.

llvm-svn: 45500

llvm-svn: 45429

llvm-svn: 45419

llvm-svn: 45414

output of nm.

llvm-svn: 45341